T. J. Grasby

Diffusion of boron in germanium at 800–900°C

Diffusion of B in Ge is studied in the temperature range 800–900°C using implantation doping and B doped epitaxial Ge layers. Concentration profiles before and after furnace annealing were obtained using high resolution secondary ion mass spectroscopy (SIMS). Diffusion coefficients were calculated by fitting the annealed profiles using TSUPREM. We obtained diffusivity values which are at least two orders of magnitude lower than the lowest values previously reported in the literature. Using our values an activation energy of 4.65(±0.3)eV is calculated. Present experimental results suggest that interstitial mediated mechanism should be considered for B diffusion in Ge in accordance with recent theoretical calculations. Annealed SIMS profiles also suggest that B solid solubility in Ge is ∼2×1018cm−3 at 875°C which agrees with literature values.

Effective mobilities in pseudomorphic Si/SiGe/Si p-channel metal-oxide-semiconductor field-effect transistors with thin silicon capping layers

The room-temperature effective mobilities of pseudomorphic Si/Si0.64Ge0.36/Si p-metal-oxidesemiconductor field effect transistors are reported. The peak mobility in the buried SiGe channel increases with silicon cap thickness. It is argued that SiO2/Si interface roughness is a major source of scattering in these devices, which is attenuated for thicker silicon caps. It is also suggested that segregated Ge in the silicon cap interferes with the oxidation process, leading to increased SiO2/Si interface roughness in the case of thin silicon caps.

Characterization and modeling of n-n Si/SiC heterojunction diodes

In this paper we investigate the physical and electrical properties of silicon layers grown by molecular beam epitaxy on 4H-SiC substrates, evaluating the effect of the Si doping, Si temperature deposition, and SiC surface cleaning procedure. Si∕SiC monolithic integration of Si circuits with SiC power devices can be considered as an attractive proposition and has the potential to be applied to a broad range of applications. X-ray diffraction and scanning electron microscopy are used to determine the Si crystal structure (cubic silicon) and morphology. I-V and C-V measurements are performed to evaluate the rectifying diode characteristics along with the Si∕SiC built-in potential and energy band offsets. In the last section, we propose that our Si∕SiC heteojunction diode current characteristics can be explained by an isojunction drift-diffusion and thermoionic emission model where the effect of doping concentration of the silicon layer and its conduction band offset with SiC is analyzed.

High conductance Ge p-channel heterostructures realized by hybrid epitaxial growth

Strained Ge p-channel heterostructures have been realized by hybrid-epitaxial growth. Strain-tuning Si0.4Ge0.6 virtual substrates were grown by ultra-high vacuum chemical vapour deposition and active layers were deposited by solid-source molecular beam epitaxy at low temperature. Following ex situ annealing, Hall effect measurements revealed a hole mobility of 1900 cm2 V−1 s−1 at 300 K (27 000 cm2 V−1 s−1 at 10 K), with a density of 1.8 × 1012 cm−2, giving a conductance in excess of current Ge heterostructures. Using a maximum-entropy mobility-spectrum analysis, 1.0 × 1012 cm−2 of these holes were found to have a mobility of 2700 cm2 V−1 s−1 at 300 K.

Growth temperature dependence for the formation of vacancy clusters in Si/Si0.64Ge0.36/Si structures

The incorporation of vacancy clusters and vacancy point defects during the growth of Si/Si0.64Ge0.36/Si structures has been observed for growth temperatures between 250 °C and 550 °C using positron annihilation spectroscopy. A strong correlation between the electrical characteristics of the structures and the size and concentration of the clusters is observed. For the onset of two-dimensional hole gas behavior, a defect concentration less than 5×1016 cm−3 is required. A further reduction in concentration below 1×1016 cm−3 results in optimum electrical performance. The depth at which defects are observed increases with decreasing growth temperature indicating defect mobility during growth or subsequent annealing.

High doped MBE Si p-n and n-n heterojunction diodes on 4H-SiC

The physical and electrical properties of heavily doped silicon (5x10^1^9cm^-^3) deposited by molecular beam epitaxy (MBE) on 4H-SiC are investigated in this paper. Silicon layers on silicon carbide have a broad number of potential applications including device fabrication or passivation when oxidised. In particular, Si/SiC contacts present several atractive material advantages for the semiconductor industry and especially for SiC processing procedures for avoiding stages such as high temperature contact annealing or SiC etching. Si films of 100nm thickness have been grown using a MBE system after different cleaning procedures on n-type (0001) Si face 8^o off 4H-SiC substrates. Isotype (n-n) and an-isotype (p-n) devices were fabricated at both 500 and 900^oC using antimonium (Sb) or boron (B), respectively. X-ray diffraction analysis (XRD) and scanning electronic mircorscope (SEM) have been used to investigate the crystal composition and morphology of the deposited layers. The electrical mesurements were performed to determine the rectifiying contact characteristics and band offsets.

Misfit strain relaxation and dislocation formation in supercritical strained silicon on virtual substrates

Relaxation of strained silicon on 20% linear graded virtual substrates was quantified using high resolution x-ray diffraction and a defect etching technique. The thickness of strained silicon was varied between 10 and 180nm. Relaxation was observed in layers below the critical thickness but increased to only 2% relaxation in the thickest layers even with annealings up to 950°C. Cross-sectional transmission electron microscopy revealed stacking faults present in layers thicker than 25nm, and nucleated 90° Shockley partial dislocations forming microtwins in the thickest layer. These features are implicated in the impediment of the relaxation process.

Terrace grading of SiGe for high-quality virtual substrates

Silicon germanium (SiGe) virtual substrates of final germanium composition x = 0.50 have been fabricated using solid-source molecular beam epitaxy with a thickness of 2 µm. A layer structure that helps limit the size of dislocation pileups associated with the modified Frank–Read dislocation multiplication mechanism has been studied. It is shown that this structure can produce lower threading dislocation densities than conventional linearly graded virtual substrates. Cross-sectional transmission electron microscopy shows the superior quality of the dislocation network in the graded regions with a lower rms roughness shown by atomic force microscopy. X-ray diffractometry shows these layers to be highly relaxed. This method of Ge grading suggests that high-quality virtual substrates can be grown considerably thinner than with conventional grading methods.

Technique for producing highly planar Si/SiO0.64Ge0.36/Si metal–oxide–semiconductor field effect transistor channels

Si/Si0.64Ge0.36/Si heterostructures have been grown at low temperature (450 °C) to avoid the strain-induced roughening observed for growth temperatures of 550 °C and above. The electrical properties of these structures are poor, and thought to be associated with grown-in point defects as indicated in positron annihilation spectroscopy. However, after an in situ annealing procedure (800 °C for 30 min) the electrical properties dramatically improve, giving an optimum 4 K mobility of 2500 cm2 V – 1 s – 1 for a sheet density of 6.2 × 1011 cm – 2. The low temperature growth yields highly planar interfaces, which are maintained after anneal as evidenced from transmission electron microscopy. This and secondary ion mass spectroscopy measurements demonstrate that the metastably strained alloy layer can endure the in situ anneal procedure necessary for enhanced electrical properties. Further studies have shown that the layers can also withstand a 120 min thermal oxidation at 800 °C, commensurate with metal–oxide–semiconductor device fabrication.

Influence of regrowth conditions on the hole mobility in strained Ge heterostructures produced by hybrid epitaxy

Strained Ge p-channel heterostructures have been produced using a hybrid-epitaxy method, which allows the advantages offered by different growth techniques to be exploited. Chemical vapor deposition of thick strain-tuned virtual substrates has been combined with growth of the active layers by solid-source molecular beam epitaxy. This paper discusses optimization of the regrowth conditions, to achieve a high hole mobility, and correlates structural characterization with electrical measurements. Initial ex situ chemical cleaning of the virtual substrate was found to be essential for successful regrowth. Structural analysis, using cross-sectional transmission electron microscopy and atomic force microscopy, showed that the regrowth temperature significantly affects the growth mode of the active layers and that planar growth was only achieved below 400°C. Samples with Ge channels from 8to30nm thick were analyzed with plan view transmission electron microscopy to study the formation of misfit dislocations and ...