M. J. Prest

Effective mobilities in pseudomorphic Si/SiGe/Si p-channel metal-oxide-semiconductor field-effect transistors with thin silicon capping layers

The room-temperature effective mobilities of pseudomorphic Si/Si0.64Ge0.36/Si p-metal-oxidesemiconductor field effect transistors are reported. The peak mobility in the buried SiGe channel increases with silicon cap thickness. It is argued that SiO2/Si interface roughness is a major source of scattering in these devices, which is attenuated for thicker silicon caps. It is also suggested that segregated Ge in the silicon cap interferes with the oxidation process, leading to increased SiO2/Si interface roughness in the case of thin silicon caps.

Strain dependence of electron-phonon energy loss rate in many-valley semiconductors

We demonstrate significant modification of the electron-phonon energy loss rate in a many-valley semiconductor system due to lattice mismatch induced strain. We show that the thermal conductance from the electron system to the phonon bath in strained n+Si, at phonon temperatures between 200 and 480 mK, is more than an order of magnitude lower than that for a similar unstrained sample.

Strain enhanced electron cooling in a degenerately doped semiconductor

Enhanced electron cooling is demonstrated in a strained-silicon/superconductor tunnel junction refrigerator of volume 40 μm3. The electron temperature is reduced from 300 mK to 174 mK, with the enhancement over an unstrained silicon control (300 mK–258 mK) being attributed to the smaller electron-phonon coupling in the strained case. Modeling and the resulting predictions of silicon-based cooler performance are presented. Further reductions in the minimum temperature are expected if the junction sub-gap leakage and tunnel resistance can be reduced. However, if only tunnel resistance is reduced, Joule heating is predicted to dominate.

Electrical isolation of dislocations in Ge layers on Si(001) substrates through CMOS-compatible suspended structures

Abstract Suspended crystalline Ge semiconductor structures are created on a Si(001) substrate by a combination of epitaxial growth and simple patterning from the front surface using anisotropic underetching. Geometric definition of the surface Ge layer gives access to a range of crystalline planes that have different etch resistance. The structures are aligned to avoid etch-resistive planes in making the suspended regions and to take advantage of these planes to retain the underlying Si to support the structures. The technique is demonstrated by forming suspended microwires, spiderwebs and van der Pauw cross structures. We finally report on the low-temperature electrical isolation of the undoped Ge layers. This novel isolation method increases the Ge resistivity to 280 Ω cm at 10 K, over two orders of magnitude above that of a bulk Ge on Si(001) layer, by removing material containing the underlying misfit dislocation network that otherwise provides the main source of electrical conduction.

Si/Si(0.64)Ge(0.36)/Si pMOSFETs with Enhanced Voltage Gain and Low 1/f Noise

Si/Si0.64Fe0.36/Si p MOSFETs with written gate lengths in the range 0.5mu micron to 10mu micron have been fabricated in a reduced thermal budget variant of a standard CMOS process. The devices exhibit enhanced maximum voltage-gains and reduced 1/f noise as compared to silicon controls.

Low-frequency noise mechanisms in Si and pseudomorphic SiGe p-channel field-effect transistors

Measurements of low frequency noise in Si and Si0.64Ge0.36 p-channel metal oxide semiconductor field effect transistors are compared with a model of carrier number fluctuations due to tunneling into an energy independent density of oxide trap states (Nox) and associated mobility fluctuations. The failure of the model to explain the data leads us to suggest that reduced noise in the SiGe device as compared to Si is primarily associated with an energy dependence of Nox and a displacement of the Fermi level at the SiO2 interface in the heterostructure relative to the Si control.

Enhanced Velocity Overshoot and Transconductance in Si/Si(0.64)Ge(0.36)/Si pMOSFETs - Predictions for Deep Submicron Devices

Electrical measurements have been carried out on Si/Si 0.64 Ge 0.36/Si pMOS devices and it is demonstrated that enhanced low field carrier mobilities lead to concomitant and substantial enhancements in velocity overshoot and transconductance at deep submicron channel lengths. This provides considerable motivation for incorporating SiGe into Si MOS technology.

Interfacial Engineering of Semiconductor-Superconductor Junctions for High Performance Micro-Coolers.

The control of electronic and thermal transport through material interfaces is crucial for numerous micro and nanoelectronics applications and quantum devices. Here we report on the engineering of the electro-thermal properties of semiconductor-superconductor (Sm-S) electronic cooler junctions by a nanoscale insulating tunnel barrier introduced between the Sm and S electrodes. Unexpectedly, such an interface barrier does not increase the junction resistance but strongly reduces the detrimental sub-gap leakage current. These features are key to achieving high cooling power tunnel junction refrigerators, and we demonstrate unparalleled performance in silicon-based Sm-S electron cooler devices with orders of magnitudes improvement in the cooling power in comparison to previous works. By adapting the junctions in strain-engineered silicon coolers we also demonstrate efficient electron temperature reduction from 300 mK to below 100 mK. Investigations on junctions with different interface quality indicate that the previously unexplained sub-gap leakage current is strongly influenced by the Sm-S interface states. These states often dictate the junction electrical resistance through the well-known Fermi level pinning effect and, therefore, superconductivity could be generally used to probe and optimize metal-semiconductor contact behaviour.

A strained silicon cold electron bolometer using Schottky contacts

We describe optical characterisation of a Strained Silicon Cold Electron Bolometer (CEB), operating on a

Silicon comb-drive actuators for low-temperature tuning of superconducting microwave circuits

350~\mathrm{mK}