A. Pezzotta

A 33 MHz 70 dB-SNR Super-Source-Follower-Based Low-Pass Analog Filter

In this paper, a 4th-order low-pass continuous-time analog filter is presented, that is implemented with the cascade of two efficient and compact biquadratic cells, realized using the Super-Source-Follower topology. The biquadratic cell uses only two capacitors and four transistors: two transistors for the signal processing and two transistors as current sources for biasing purpose. The 4th-order filter prototype has been integrated in 0.18 μm CMOS technology. For a 33 MHz cut-off frequency, the filter performs 18 dBm-IIP3 for two tones at 2 MHz and 3 MHz, with total current of 770 μA from a single 1.8 V supply voltage.

4 th -Order 84dB-DR CMOS-90nm low-pass filter for WLAN receivers

In this paper a 11MHz-f@−3dB continuous-time analog filter is presented. A low-noise circuital topology has been used based on typical Active-RC cells, like opamp-based integrators, and Active-Gm-RC biquadratic cell. The basic idea is to synthesize two complex poles pairs (4th-Order Filter) using a single compact Active RC cell, which minimizes the in-band noise power contributions. A filter prototype, complying with WLAN baseband requirements, has been designed in CMOS 90nm technology. Thanks to noise power spectral density reduction − 48µVrms output integrated noise (100kHz÷11MHz) at 0dB-pass-band gain - wide Dynamic Range (84dB@THD>40dBc) is performed. In-band IIP3 is 10dBm, while the filter power consumption is 14mW.

A 4.3μW 28nm-CMOS pixel front-end with switched inverter-based comparator

The complete design and electrical characterization of a readout frontend for high luminosity pixel detectors is hereby presented. The design has been carried out in 28nm bulk-CMOS technology. The selected technology process shows significant advantages in terms of radiation hardness, faster/low-power digital signal processing and whole chip area reduction. Nonetheless, it is challenging in terms of operating point (0.9V supply voltage at 0.5V threshold voltage for standard process transistors), dynamic range, and large sensitivity to Process-Voltage-Temperature variations. The proposed integrated circuit includes the cascade of a low-noise preamplifier stage and a switched-capacitor inverter-based comparator. The overall system detects input charges up to 14fC and provides information about the amount of the charge with a Time-over-Threshold (ToT) technique. It features 4.3μW power consumption, 54dB Signal Noise Ratio and 0.02mm2 area occupancy. A ToT range of 180ns in 28nm bulk-CMOS represents a challenge for the future Time-to-Digital Converters (TDC) used in High-Energy-Physics readout systems. Analog front-end and TDC development anticipate a higher charge quantization resolution in the next physics experiments.

IC-PIX28: A 28nm read-out channel for pixel detector

An Integrated Chip prototype for PIXel read-out, named IC-PIX28 and designed in 28nm CMOS technology, is here presented. The chip features a single channel including a cascade of a Charge-Sensitive-Amplifier (CSA) and a comparator, performing a Time-over-Threshold (ToT) operation. The IC-PIX28 comparator can operate with thresholds ≥3mV, generated on-chip starting from an off-chip reference voltage. A few number of transistors allows processing an input charge within 0.1fC÷5fC range. With the minimum input charge, the CSA output peak voltage is 4.6mV reached in 11ns. In this condition, 44mV/fC sensitivity and 0.029fC (180e-) Equivalent-Noise-Charge (ENC) are achieved with 4.67μA current consumption and 0.07mm2 area occupancy.

A CMOS 0.13μm read-out front-end for Triple-Gas-Electron-Multiplier detectors

In this paper a dedicated integrated front-end for the Triple-GEM (Gas Electron Multiplier) detector is presented. The design has been realized in 0.13 μm CMOS technology. This system aims to improve performance with respect to the state-of-the-art on these types of detectors, regarding adaptability, portability, power consumption and on-chip data processing. The front-end is composed by 8-input-channels. Each channel performs the charge-vs-time conversion, and then the signal is definitively converted into digital domain. For this aim a Charge-Sensitive Preamplifier (CSP), and a Charge-to-Time Converter (CTC) are implemented. An automatic on-chip calibration circuit is also included, in order to compensate CMOS technological process/temperature variations. The system is able to manage a 15 pF detector capacitance. The maximum count rate is 4·106 counts-per-second (cps) and the power consumption is 3.8 mW/ch. The Equivalent Noise Charge (ENC) is 418 e-. The front-end compares favorably with the state-of-the-art.

A CMOS 0.13µm low power front-end for GEM detectors

A low power front-end for GEM (Gas Electron Multiplier) detectors has been developed in 0.13μm CMOS node. The front-end sensitivity is 0.5mV/fC which remains almost unchanged up to a 15 pF detector parasitic capacitance. The input dynamic charge range varies from 30fC to 1pC including only a single (negative) polarity charge. The front-end provides as output signal two different time-domain square-wave signals. The first one indicates the charge detection event and the second one the amount of charge (providing a time-domain impulse, whose duty-cycle is proportional to the effective charge read by the front-end). Proper automatic calibration circuits are then implemented in order to optimize the front-end performance in case of CMOS process and temperature variations. The power consumption is 3.8mW, against 12mW in the existing market solutions [9]. A feed-forward opamp architecture has been exploited in analog part of read-out channel, in order to improve speed and time-response slope.

GEMINI: A triple-GEM detector read-out mixed-signal ASIC in 180nm CMOS

This paper presents GEMINI, an entire read-out System-on-Chip (SoC) to be used with the Triple Gas-Electron Multiplier (GEM) detector. Designed in CMOS 180 nm technology, GEMINI pushes towards the state-of-the-art for this peculiar detector front-end, as regards the count rate and detector pixel parasitic capacitance sustainability. It is composed of 16 channels, each performing a charge-to-voltage conversion via a Charge-Sensitive Preamplifier (CSP), a successive event discrimination with channel-independent threshold and an event-triggered reset. The CSP analog output and the LVDS discriminator output are available as chip outputs for each channel. The Q-to-V conversion accuracy is guaranteed by an automatic on-chip calibration unit, compensating for environmental, CMOS process and supply voltage variations. GEMINI is able to sustain a 5 Mcps count rate, managing up to 40 pF pixel capacitance and with a 2.7mW/ch power consumption.

A 30MHz 28dBm-IIP3 3.2mW fully-differential Sallen-Key 4 th -order filter with out-of-band zeros cancellation

In this paper a 4th-order 30MHz Butterworth low-pass analog filter is presented, exploiting the Sallen-Key (SK) biquadratic cell circuit. The out-of-band zeros typically present in SK cells, are cancelled by using a low-power auxiliary path, resulting in a significant improvement of the stopband rejection, at the cost of a small power budget for the same auxiliary path biasing. An efficient unity gain buffer has been used, based on super-source-follower stage, providing very large in-band IIP3 over the entire filter bandwidth (21.5dBm for 25MHz&26MHz input tones), at 3.2mW power consumption from a single 1.8V supply voltage. The filter prototype has been designed in CMOS 0.18μm tech. The total area occupancy is 0.12mm2, the in-band integrated noise is 197μVRMS.

A rail-to-rail-input chopper instrumentation amplifier in 28nm CMOS

This paper presents a chopper instrumentation amplifier designed in 28nm CMOS technology. The operational amplifier has a rail-to-rail folded cascode input stage, which ensures a constant gm over the available common-mode range. It is characterized by a Nested Miller compensation. All transistors operate in sub-threshold region; thus the opamp has been designed through a specific procedure for sub-threshold operation. The chopper technique is exploited to reduce the input referred offset and noise. The circuit operates with 0.9V supply voltage and exhibits a simulated 106dB DC gain and 329kHz GBW. Montecarlo simulations demonstrate an offset distribution with 2.2μV standard deviation. The input noise spectral density is equal to 27nV/√Hz, giving a noise efficiency factor of 8.

A 1.25mW 3 rd -order Active-G m -RC 250MHz-bandwidth analog filter based on power-stability optimization

In this paper a 250MHz-bandwidth continuous-time low-pass filter is presented. The filter is based on Active-Gm-RC biquadratic cell. With respect to Active-Gm-RC, this filter exploits an additional input RC-net, increasing the low-pass filtering order up to 3, while maintaining single-Opamp topology. In particular, Opamp frequency response has been optimized, exploiting a proper algorithm, that allows to minimize power and maximize loop gain phase margin. A prototype of the filter has been designed in CMOS 0.13μm technology, complying with ultra-wide-band receivers specifications. The filter consumes 1.2mW, while processing a 0.7Vzero-peak differential signal, and maintaining noise power spectral density under 237μVrms. The overall Signal-to-Noise-Ratio is 65dB.