F. Resta

A 4.3μW 28nm-CMOS pixel front-end with switched inverter-based comparator

The complete design and electrical characterization of a readout frontend for high luminosity pixel detectors is hereby presented. The design has been carried out in 28nm bulk-CMOS technology. The selected technology process shows significant advantages in terms of radiation hardness, faster/low-power digital signal processing and whole chip area reduction. Nonetheless, it is challenging in terms of operating point (0.9V supply voltage at 0.5V threshold voltage for standard process transistors), dynamic range, and large sensitivity to Process-Voltage-Temperature variations. The proposed integrated circuit includes the cascade of a low-noise preamplifier stage and a switched-capacitor inverter-based comparator. The overall system detects input charges up to 14fC and provides information about the amount of the charge with a Time-over-Threshold (ToT) technique. It features 4.3μW power consumption, 54dB Signal Noise Ratio and 0.02mm2 area occupancy. A ToT range of 180ns in 28nm bulk-CMOS represents a challenge for the future Time-to-Digital Converters (TDC) used in High-Energy-Physics readout systems. Analog front-end and TDC development anticipate a higher charge quantization resolution in the next physics experiments.

IC-PIX28: A 28nm read-out channel for pixel detector

An Integrated Chip prototype for PIXel read-out, named IC-PIX28 and designed in 28nm CMOS technology, is here presented. The chip features a single channel including a cascade of a Charge-Sensitive-Amplifier (CSA) and a comparator, performing a Time-over-Threshold (ToT) operation. The IC-PIX28 comparator can operate with thresholds ≥3mV, generated on-chip starting from an off-chip reference voltage. A few number of transistors allows processing an input charge within 0.1fC÷5fC range. With the minimum input charge, the CSA output peak voltage is 4.6mV reached in 11ns. In this condition, 44mV/fC sensitivity and 0.029fC (180e-) Equivalent-Noise-Charge (ENC) are achieved with 4.67μA current consumption and 0.07mm2 area occupancy.

A 30MHz 28dBm-IIP3 3.2mW fully-differential Sallen-Key 4 th -order filter with out-of-band zeros cancellation

In this paper a 4th-order 30MHz Butterworth low-pass analog filter is presented, exploiting the Sallen-Key (SK) biquadratic cell circuit. The out-of-band zeros typically present in SK cells, are cancelled by using a low-power auxiliary path, resulting in a significant improvement of the stopband rejection, at the cost of a small power budget for the same auxiliary path biasing. An efficient unity gain buffer has been used, based on super-source-follower stage, providing very large in-band IIP3 over the entire filter bandwidth (21.5dBm for 25MHz&26MHz input tones), at 3.2mW power consumption from a single 1.8V supply voltage. The filter prototype has been designed in CMOS 0.18μm tech. The total area occupancy is 0.12mm2, the in-band integrated noise is 197μVRMS.

A rail-to-rail-input chopper instrumentation amplifier in 28nm CMOS

This paper presents a chopper instrumentation amplifier designed in 28nm CMOS technology. The operational amplifier has a rail-to-rail folded cascode input stage, which ensures a constant gm over the available common-mode range. It is characterized by a Nested Miller compensation. All transistors operate in sub-threshold region; thus the opamp has been designed through a specific procedure for sub-threshold operation. The chopper technique is exploited to reduce the input referred offset and noise. The circuit operates with 0.9V supply voltage and exhibits a simulated 106dB DC gain and 329kHz GBW. Montecarlo simulations demonstrate an offset distribution with 2.2μV standard deviation. The input noise spectral density is equal to 27nV/√Hz, giving a noise efficiency factor of 8.

A 28.8-MHz 23-dBm-IIP3 3.2-mW Sallen-Key Fourth-Order Filter With Out-of-Band Zeros Cancellation

In this brief, a 28.8-MHz -3-dB frequency low-pass analog filter is presented. The filter synthesizes a fourth-order Butterworth transfer function, exploiting the well-known Sallen-Key (SK) biquadratic cell. The out-of-band zeros typically present in SK implementations are hereby completely canceled by using a low-power auxiliary path. This leads to a significant improvement of the stop-band rejection, at the cost of a small power for the same auxiliary path biasing. The design exhibits very large in-band IIP3 over the entire filter bandwidth (20 dBm at 10 MHz and 11 MHz), at 3.2-mW power consumption. The filter prototype has been designed in CMOS 0.18-μm technological node. The total area occupancy is 0.12 mm2 and the in-band integrated noise is 101 μVRMS.

1GigaRad TID impact on 28 nm HEP analog circuits

The Total Ionizing Dose (TID) levels foreseen after the future upgrade of the CERN Large Hadron Collider (High Luminosity LHC) will heavily influence the performance of the electronics. A TID level of 1GigaRad will be accumulated in the innermost layer of the pixel detector in 10 years of operations, which could damage the readout circuits behavior with important failures in the experiments. To prevent this situation, the choice of a proper technology for the readout ASICs represents a key point. This paper deals with the characterization of single transistors and of an analog circuit, both realized in a TSMC 28nm bulk CMOS technology, after being irradiated with 1 GigaRad TID. nMOS devices result more resistant than pMOS showing a weak degradation of the electrical parameters. Nevertheless, the considerable leakage current increment is not negligible because it could affect analog circuits as that hereby presented. In the proposed analog circuit, the high radiation level induces a 20% gain reduction and an 80% slowdown of the Charge Sensitive Preamplifier time response.

A 28.8MHz 21.1dBm-IIP3 3.2mW Sallen-Key 4th-Order filter with out-of-band zeros cancellation

A 4th-order 28.8MHz low-pass analog filter uses a modified version of Sallen-Key (SK) biquad that solves the standard SK cell critical aspect due to the out-of-band zeros (OoB). The proposed cell completely cancel the OoB zeros by means of a low-power auxiliary path and a specific design optimization.

A 22.5MHz 21.5dBm-IIP3 4 th -Order FLFB analog filter

A 4th-order single-loop Follow-the-Leader-Feedback (FLFB) low-pass filter is hereby presented. The outstanding FLFB noise behavior has been exploited to release a specific power budget for linearity performance enhancement. Moreover, two pairs of complex poles are synthesized by using a single compact Active-RC cell, avoiding cascade of two or more stages (typically needed for high order filters), and relaxing this way noise power constraints. A prototype of the filter has been integrated in CMOS 0.18μm technological node, having 22.5MHz -3dB low-pass frequency. 21.5dBm in-band IIP3 and 76μVRMS input referred in-band integrated noise have been achieved. The SNR for a -40dB-THD is 69dB. The power consumption is 7mA. The efficiency of the hereby proposed technique is demonstrated by the very high Figure-of-Merit (160J-1) achieved by the FLFB filter comparing with the Active-RC filters state-of-the-art.

Performance of the new Amplifier-Shaper-Discriminator chip for the ATLAS MDT chambers at the HL-LHC

The Phase-II Upgrade of the ATLAS Muon Detector requires new electronics for the readout of the MDT drift tubes. The first processing stage, the Amplifier-Shaper-Discriminator (ASD), determines the performance of the readout for crucial parameters like time resolution, gain uniformity, efficiency and noise rejection. An 8-channel ASD chip, using the IBM 130 nm CMOS 8RF-DM technology, has been designed, produced and tested. The area of the chip is 2.2 × 2.9 square mm size. We present results of detailed measurements as well as a comparision with simulation results of the chip behaviour at three different levels of detail.

An 8-channels O.13μm-CMOS front-end for ATLAS MDT-detectors

An 8-channels read-out front-end for LHC ATLAS Muon-Drift-Tubes detectors is presented (8xAFE). The system is composed by the cascade of the analog signal processing FrontEnd and of the Wilkinson A/D (to perform voltage-to-time conversion for time-over-threshold detection). The sensitivity at the output of the analog signal processing chain is 13.8mV/fC, while the Equivalent-Noise-Charge (ENC) is 0.6fC (~3.38ke), performing <;12ns preamplifier rise-time. These performances have been achieved, managing very high detector parasitic capacitance at the front-end input (~60pF). Each channel consumes 11mA from a single 3.3V supply voltage. In 0.13μm CMOS, the total area occupancy is 6.3mm2.