A. R. Long

Origin of switching noise in GaAs/AlxGa1-xAs lateral gated devices

We have studied switching (telegraph) noise at low temperature in

Monte Carlo Simulations of High-Performance Implant Free In

\mathrm{Ga}\mathrm{As}∕{\mathrm{Al}}_{x}{\mathrm{Ga}}_{1\ensuremath{-}x}\mathrm{As}

_{0.3}

heterostructures with lateral gates and introduced a model for its origin, which explains why noise can be suppressed by cooling samples with a positive bias on the gates. The noise was measured by monitoring the conductance fluctuations around

Ga

{e}^{2}∕h

_{0.7}

on the first step of a quantum point contact at around

As Nano-MOSFETs for Low-Power CMOS Applications

1.2\phantom{\rule{0.3em}{0ex}}\mathrm{K}

Commensurability oscillations due to pinned and drifting orbits in a two-dimensional lateral surface superlattice

. Cooling with a positive bias on the gates dramatically reduces this noise, while an asymmetric bias exacerbates it. Our model is that the noise originates from a leakage current of electrons that tunnel through the Schottky barrier under the gate into the conduction band and become trapped near the active region of the device. The key to reducing noise is to keep the barrier opaque under experimental conditions. Cooling with a positive bias on the gates reduces the density of ionized donors. This builds in an effective negative gate voltage so that a smaller negative bias is needed to reach the desired operating point. This suppresses tunneling from the gate and hence the noise. The reduction in the density of ionized donors also strengthens the barrier to tunneling at a given applied voltage. Further support for the model comes from our direct observation of the leakage current into a closed quantum dot, around

Anharmonic periodic modulation in lateral surface superlattices

{10}^{\ensuremath{-}20}\phantom{\rule{0.3em}{0ex}}\mathrm{A}

Gadolinium gallium oxide/gallium oxide insulators on GaAs and In0.53Ga0.47As n+ MOS capacitors: The interface state model and beyond

for this device. The current was detected by a neighboring quantum point contact, which showed monotonic steps in time associated with the tunneling of single electrons into the dot. If asymmetric gate voltages are applied, our model suggests that the noise will increase as a consequence of the more negative gate voltage applied to one of the gates to maintain the same device conductance. We observe exactly this behavior in our experiments.

A simple model for the characteristics of GaAs/AlGaAs modulation-doped devices

The potential performance of implant free heterostructure In0.3Ga0.7As channel MOSFETs with gate lengths of 30, 20, and 15 nm is investigated using state-of-the-art Monte Carlo (MC) device simulations. The simulations are carefully calibrated against the electron mobility and sheet density measured on fabricated III-V MOSFET structures with a high-kappa dielectric. The MC simulations show that the 30 nm gate length implant free MOSFET can deliver a drive current of 2174 muA/mum at 0.7 V supply voltage. The drive current increases to 2542 muA/mum in the 20 nm gate length device, saturating at 2535 muA/mum in the 15 nm gate length one. When quantum confinement corrections are included into MC simulations, they have a negligible effect on the drive current in the 30 and 20 nm gate length transistors but lower the 15 nm gate length device drive current at 0.7 V supply voltage by 10%. When compared to equivalent Si based MOSFETs, the implant free heterostructure MOSFETs can deliver a very high performance at low supply voltage, making them suitable for low-power high-performance CMOS applications