P. Longo

Experimental evaluation of interfaces using atomic-resolution high angle annular dark field (HAADF) imaging

Aberration-corrected high angle annular dark field (HAADF) imaging in scanning transmission electron microscopy (STEM) can now be performed at atomic-resolution. This is an important tool for the characterisation of the latest semiconductor devices that require individual layers to be grown to an accuracy of a few atomic layers. However, the actual quantification of interfacial sharpness at the atomic-scale can be a complicated matter. For instance, it is not clear how the use of the total, atomic column or background HAADF signals can affect the measured sharpness or individual layer widths. Moreover, a reliable and consistent method of measurement is necessary. To highlight these issues, two types of AlAs/GaAs interfaces were studied in-depth by atomic-resolution HAADF imaging. A method of analysis was developed in order to map the various HAADF signals across an image and to reliably determine interfacial sharpness. The results demonstrated that the level of perceived interfacial sharpness can vary significantly with specimen thickness and the choice of HAADF signal. Individual layer widths were also shown to have some dependence on the choice of HAADF signal. Hence, it is crucial to have an awareness of which part of the HAADF signal is chosen for analysis along with possible specimen thickness effects for future HAADF studies performed at the scale of a few atomic layers.

GdGaO: A gate dielectric for GaAs metal-oxide-semiconductor field-effect transistors

GdxGa0.4−xO0.6∕Ga2O3 dielectric stacks have been grown on (001)GaAs to form a III-V∕oxide with a low interface state density and a high conduction band offset. Photoluminescence is used to compare the stacks with low interface state density Ga2O3–GaAs layers. Rutherford backscattering and electron energy loss spectroscopy are used to investigate the Gd compositional variation with depth and this is related to the interface state density. The effect of Gd flux and atomic oxygen on the growth rate is reported. The leakage current through GdxGa0.4−xO0.6∕Ga2O3 stacks is compared with ones using only Ga2O3 as the oxide.

Gallium oxide and gadolinium gallium oxide insulators on Si δ-doped GaAs/AlGaAs heterostructures

Test devices have been fabricated on two specially grown GaAs/AlGaAs wafers with 10 nm thick gate dielectrics composed of either Ga2O3 or a stack of Ga2O3 and Gd0.25Ga0.15O0.6. The wafers have two GaAs transport channels either side of an AlGaAs barrier containing a Si δ-doping layer. Temperature dependent capacitance-voltage (C-V) and current-voltage (I-V) studies have been performed at temperatures between 10 and 300 K. Bias cooling experiments reveal the presence of DX centers in both wafers. Both wafers show a forward bias gate leakage that is by a single activated channel at higher temperatures and by tunneling at lower temperatures. When Gd0.25Ga0.15O0.6 is included in a stack with 1 nm of Ga2O3 at the interface, the gate leakage is greatly reduced due to the larger band gap of the Gd0.25Ga0.15O0.6 layer. The different band gaps of the two oxides result in a difference in the gate voltage at the onset of leakage of ∼3 V. However, the inclusion of Gd0.25Ga0.15O0.6 in the gate insulator introduces man...

A TEM nanoanalytical investigation of Pd/Ge ohmic contacts for the miniaturization and optimization of n-InGaAs MOSFET devices

In this paper, a nanoanalytical investigation of electron beam evaporated PdGe ohmic contacts onto an n+ In0.53Ga0.47As layer using electron energy loss spectroscopy (EELS) is presented. The chemical information reported in this paper has been obtained using EELS spectrum images (SI) that allow not only depth resolution but also spatial resolution which is essential in such inhomogeneous systems.

Elemental Profiling of III-V MOSFET High- k Dielectric Gate Stacks Using EELS Spectrum Imaging

In this paper a quantitative determination of the elemental distribution across a GaAs/Ga2O3/GGO dielectric gate stack is presented and the analysis discussed. The EELS spectrum imaging technique is described and the data analysis discussed.

Deep sub-micron and self-aligned flatband III–V MOSFETs

We report various flatband III–V MOSFETs with an In<inf>0.3</inf>Ga<inf>0.7</inf>As channel and Ga<inf>2</inf>O<inf>3</inf>/GaGdO (GGO) (κ=20) gate dielectric stack. Lithographically aligned devices display sub-threshold slope (S) of 60–70 mV/dec for gate lengths down to 100 nm, the lowest values reported to date. We also present the first 100 nm gate length enhancement mode, fully self-aligned III–V MOSFETs realized using critical geometry modules compatible with silicon VLSI manufacturing.

An EELS sub-nanometer investigation of the dielectric gate stack for the realization of InGaAs based MOSFET devices

In this paper, a subnanometer investigation of the Ga2O3/GdGaO dielectric gate stack deposited onto InGaAs is presented. Results regarding the influence of the growth conditions on the interface region from a chemical and morphological point of view are presented. The chemical information reported in this paper has been obtained using electron energy loss spectroscopy (EELS) that was carried out in a scanning transmission electron microscope ((S)TEM) showing both spatial and depth resolution.

Nanoanalytical investigation of the dielectric gate stack for the realisation of III–V MOSFET devices

Planar Si MOSFET technology using Si(ON) is rapidly approaching its theoretical limit and the search for new material is essential. n-type GaAs has a mobility 5 times higher than Si [1]. This makes it a suitable candidate for MOSFETs devices. So far, GaAs has not been used for practical MOSFETs because of the difficulties of making a good dielectric oxide layer in terms of leakage current and unpinned Fermi Level. Using processes pioneered by Passlack et al. [2], dielectric gate stacks consisting of a template layer of amorphous Ga2O3 followed by amorphous GdGaO have been grown on GaAs substrates. Careful deposition of Ga2O3 can leave the Fermi Level unpinned. The introduction of Gd is important in order to decrease the leakage of current.

EFTEM and EELS SI: tools for investigating the effects of etching processes for III-V MOSFET devices

High quality oxides layers are now available for MOSFETs on GaAs. For successful devices, suitable process schemes are required. In this paper we show an investigation of an etching process on a GaAs/Ga2O3/GGO dielectric gate stack. This investigation has been carried out using EFTEM and EELS SI. EFTEM provides a quick analysis on the structure while EELS SI offers much better resolution and the possibility to quantitatively characterize the material.