G. W. Paterson

Electron Mobility in Surface- and Buried-Channel Flatband

In this letter, we investigate the scaling potential of flatband III-V MOSFETs by comparing the mobility of surface and buried-channel In_0.53Ga_0.47As devices employing an atomic layer-deposited Al₂O₃ gate dielectric and a delta-doped InGaAs/InAlAs/InP heterostructure. Peak electron mobilities of 4300 cm²/V · s and 6600 cm²/V · s at a carrier density of 3 × 10¹² cm^-2 were determined for the surfaceand buried-channel structures, respectively. In contrast to similarly scaled inversion-channel devices, we find that the mobility in surface channel flatband structures does not drop rapidly with the electron density, but rather high mobility is maintained up to carrier concentrations around 4 × 10¹² cm^-2 before slowly dropping to around 2000 cm²/V · s at 1 × 10¹³ cm^-2. We believe these to be world leading metrics for this material system and an important development in informing the III-V MOSFET device architecture selection process for the future low-power highly scaled CMOS.

\hbox{In}_{0.53}\hbox{Ga}_{0.47}\hbox{As}

In this letter, we investigate the scaling potential of flatband III-V MOSFETs by comparing the mobility of surface and buried-channel In_0.53Ga_0.47As devices employing an atomic layer-deposited Al₂O₃ gate dielectric and a delta-doped InGaAs/InAlAs/InP heterostructure. Peak electron mobilities of 4300 cm²/V · s and 6600 cm²/V · s at a carrier density of 3 × 10¹² cm^-2 were determined for the surfaceand buried-channel structures, respectively. In contrast to similarly scaled inversion-channel devices, we find that the mobility in surface channel flatband structures does not drop rapidly with the electron density, but rather high mobility is maintained up to carrier concentrations around 4 × 10¹² cm^-2 before slowly dropping to around 2000 cm²/V · s at 1 × 10¹³ cm^-2. We believe these to be world leading metrics for this material system and an important development in informing the III-V MOSFET device architecture selection process for the future low-power highly scaled CMOS.

MOSFETs With ALD

The application of Li7La3Zr2O12 as a Li+ solid electrolyte is hampered by the lack of a reliable procedure to obtain and densify the fast-ion conducting cubic garnet polymorph. Dense cubic Li7La3Zr2O12-type phases are typically formed as a result of Al-incorporation in an unreliable reaction with the alumina crucible at elevated temperatures of up to 1230 °C. High Al3+-incorporation levels are also believed to hinder the three-dimensional movement of Li+ in these materials. Here, a new, facile hybrid sol–gel solid-state approach has been developed in order to accomplish reliable and controllable synthesis of these phases with low Al-incorporation levels. In this procedure, sol–gel processed solid precursors of Li7La3Zr2O12 and Al2O3 nanosheets are simply mixed using a pestle and mortar and allowed to react at 1100 °C for 3 h to produce dense cubic phases. Fast-ion conducting Al-doped Li7La3Zr2O12 phases with the lowest reported Al3+-content (∼0.12 mol per formula unit), total conductivities of ∼3 × 10−4 S cm−1, bulk conductivities up to 0.6 mS and ion conduction activation energies as low as 0.27 eV, have been successfully achieved. The ease of lithium diffusion in these materials is attributed to the formation of dense cubic phases with low Al3+ dopant ratios. This approach is applicable to Li7−xLa3Zr2−xTaxO12 phases and opens up a new synthetic avenue to Li7La3Zr2O12-type materials with greater control over resulting characteristics for energy storage applications.

\hbox{Al}_{2}\hbox{O}_{3}

Amorphous zirconium oxide thin films deposited at room temperature, sandwiched between Pt and Ti electrodes, show resistive bipolar resistive switching with good overall performance figures (retention, ON/OFF ratio and durability). A variability observed during electrical characterisation is consistent with the coexistence of two different resistive switching mechanisms within the ZrO2 layer. Electron energy loss spectroscopy is used to map chemical variations across the device on the nanoscale. Partial oxidation of the Ti electrode creates an ohmic contact with zirconia and injects positively charged oxygen vacancies into the zirconia layer that are then responsible for resistive switching at the Pt / zirconia interface.

Gate Dielectric

The electrical characteristics of n+ GaAs and In0.53Ga0.47As MOS capacitors with a dielectric stack of Ga2O3/Gd0.25Ga0.15O0.6 have been examined in detail and compared to the interface state model. The deviations from the model are assessed and the limitations of different interface state density extraction techniques are highlighted. The results of a model which accounts for many of the electrical characteristics of the InGaAs material by including states within the oxide and at the interface are reported. A hypothesis that may explain the difference between the GaAs and InGaAs characteristics and the similarities between the properties of many different oxides on InGaAs is discussed, leading to suggestions on how the oxide quality may be improved.

Electron mobility in surface- and buried- channel flatband In 0.53 Ga 0.47 As MOSFETs with ALD Al 2 O 3 gate dielectric.

GdxGa0.4−xO0.6∕Ga2O3 dielectric stacks have been grown on (001)GaAs to form a III-V∕oxide with a low interface state density and a high conduction band offset. Photoluminescence is used to compare the stacks with low interface state density Ga2O3–GaAs layers. Rutherford backscattering and electron energy loss spectroscopy are used to investigate the Gd compositional variation with depth and this is related to the interface state density. The effect of Gd flux and atomic oxygen on the growth rate is reported. The leakage current through GdxGa0.4−xO0.6∕Ga2O3 stacks is compared with ones using only Ga2O3 as the oxide.

Low-temperature densification of Al-doped Li7La3Zr2O12: a reliable and controllable synthesis of fast-ion conducting garnets

Molecular beam epitaxy has been used to deposit Ga2O3 onto GaAs(001) to form a III-V/oxide interface. Photoluminescence is used to monitor the interface quality and to compare these films with samples known to have a low interface state density and an unpinned Fermi level. An additional flux of molecular oxygen has been used during oxide growth, and the impact on growth rate is reported. A rf plasma source is shown to produce mainly neutral atomic oxygen. Atomic oxygen has a significant impact on the oxide growth mechanism and interface quality. The performance of metal oxide semiconductor field effect transistors fabricated from GaAs structures with their surface unpinned by Ga2O3 is discussed briefly.

Stability, bistability and instability of amorphous ZrO2 resistive memory devices

The admittances and subthreshold characteristics of capacitors and MOSFETs on buried and surface In0.53Ga0.47As channel flatband wafers, with a dielectric of Al2O3 deposited on In0.53Ga0.47As, are reported. The admittance characteristics of both wafers indicate the presence of defect states within the oxide, in common with a number of other oxides on In0.53Ga0.47As. The two wafers studied have not been hydrogen annealed, but do show some similar features to FGA treated oxides on n+ substrates. We discuss how the possible presence of residual hydroxyl ions in as-grown Al2O3 may explain these similarities and also account for many of the changes in the properties of FGA treated n+ samples. The issues around the comparison of subthreshold swing (SS) results and the impact of transistor design parameters on the energy portion of the defect state distribution affecting efficient device switching are discussed. The interface state model is applied to low source-drain voltage SS data to extract an effective inte...

Gadolinium gallium oxide/gallium oxide insulators on GaAs and In0.53Ga0.47As n+ MOS capacitors: The interface state model and beyond

The 300-K admittance characteristics of n+ In0.53Ga0.47As MOS capacitors with a dielectric stack of Gd0.25Ga0.15O0.6/Ga2O3 in as-grown condition are examined in detail and compared to an oxide trap model that we previously introduced. The model explains many of the observed features not contained in the interface state model. By fitting the model to experimental data, we extract a distribution of defect states in space and energy within the oxide and at the oxide/semiconductor interface separately. Oxide states are the dominant defects over a wide range of energy. The defect state densities are not subject to the usual resolution limits of conventional analyses. Using this approach, it is possible to characterize relatively rapidly a wide range of energies at a single temperature without the need for reaching the low or high limits of frequency. The implications for the conventional interface state density (Dit) extraction techniques are explored. It is shown how oxide states can affect the extraction of ...

GdGaO: A gate dielectric for GaAs metal-oxide-semiconductor field-effect transistors

Test devices have been fabricated on two specially grown GaAs/AlGaAs wafers with 10 nm thick gate dielectrics composed of either Ga2O3 or a stack of Ga2O3 and Gd0.25Ga0.15O0.6. The wafers have two GaAs transport channels either side of an AlGaAs barrier containing a Si δ-doping layer. Temperature dependent capacitance-voltage (C-V) and current-voltage (I-V) studies have been performed at temperatures between 10 and 300 K. Bias cooling experiments reveal the presence of DX centers in both wafers. Both wafers show a forward bias gate leakage that is by a single activated channel at higher temperatures and by tunneling at lower temperatures. When Gd0.25Ga0.15O0.6 is included in a stack with 1 nm of Ga2O3 at the interface, the gate leakage is greatly reduced due to the larger band gap of the Gd0.25Ga0.15O0.6 layer. The different band gaps of the two oxides result in a difference in the gate voltage at the onset of leakage of ∼3 V. However, the inclusion of Gd0.25Ga0.15O0.6 in the gate insulator introduces man...