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Dive into the research topics where I.G. Thayne is active.

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Featured researches published by I.G. Thayne.


IEEE Electron Device Letters | 2007

A Planar Gunn Diode Operating Above 100 GHz

Ata Khalid; Neil John Pilgrim; G M Dunn; M. Holland; C.R. Stanley; I.G. Thayne; David R. S. Cumming

We show the experimental realization of a 108-GHz planar Gunn diode structure fabricated in GaAs/AlGaAs. There is a considerable interest in such devices since they lend themselves to integration into millimeter-wave and terahertz integrated circuits. The material used was grown by molecular beam epitaxy, and devices were made using electron beam lithography. Since the frequency of oscillation is defined by the lithographically controlled anode-cathode distance, the technology shows great promise in fabricating single chip terahertz sources.


IEEE Electron Device Letters | 2005

50-nm T-gate metamorphic GaAs HEMTs with f/sub T/ of 440 GHz and noise figure of 0.7 dB at 26 GHz

Khaled Elgaid; H. McLelland; M. Holland; David A. J. Moran; C.R. Stanley; I.G. Thayne

GaAs-based transistors with the highest f/sub T/ and lowest noise figure reported to date are presented in this letter. A 50-nm T-gate In/sub 0.52/Al/sub 0.48/As/In/sub 0.53/Ga/sub 0.47/As metamorphic high-electron mobility transistors (mHEMTs) on a GaAs substrate show f/sub T/ of 440 GHz, f/sub max/ of 400 GHz, a minimum noise figure of 0.7 dB and an associated gain of 13 dB at 26 GHz, the latter at a drain current of 185 mA/mm and g/sub m/ of 950 mS/mm. In addition, a noise figure of below 1.2 dB with 10.5 dB or higher associated gain at 26 GHz was demonstrated for drain currents in the range 40 to 470 mA/mm at a drain bias of 0.8 V. These devices are ideal for low noise and medium power applications at millimeter-wave frequencies.


Solid-state Electronics | 2002

Scaling of pseudomorphic high electron mobility transistors to decanano dimensions

K. Kalna; S. Roy; Asen Asenov; Khaled Elgaid; I.G. Thayne

The performance enhancement associated with the scaling of pseudomorphic high electron mobility transistors (PHEMTs) to deep decanano dimensions is studied using Monte Carlo (MC) simulations. The full scaling of a standard 120 nm PHEMT to gate lengths of 90, 70, 50 and 30 nm in both lateral and vertical dimensions is compared with an approach where only the lateral dimensions are scaled. The study is based on an extended transport module integrated in the finite element MC simulator H2F and accurate up to an electric field of 200 kV/cm, and on the careful calibration of MC device simulations against I–V characteristics from the real 120-nm gate length PHEMT. The fully scaled devices exhibit a continuous improvement in transconductance as channel lengths reduce while performance deteriorates in devices scaled only laterally. The contact resistances become a limiting factor to the performance of the fully scaled devices at shorter channel lengths. The microwave performance of the scaled devices is studied using the transient MC analysis.


international electron devices meeting | 2007

High Mobility III-V MOSFETs For RF and Digital Applications

Matthias Passlack; Peter Zurcher; K. Rajagopalan; R. Droopad; Jonathan K. Abrokwah; M. Tutt; Y.-B. Park; E. Johnson; O. Hartin; A. Zlotnicka; P. Fejes; R.J.W. Hill; David A. J. Moran; Xu Li; H. Zhou; D.S. Macintyre; S. Thorns; Asen Asenov; K. Kalna; I.G. Thayne

Developments over the last 15 years in the areas of materials and devices have finally delivered competitive III-V MOSFETs with high mobility channels. This paper briefly reviews the above developments, discusses properties of the GdGaO/ Ga2O3 MOS systems, presents GaAs MOSFET DC and RF data, and concludes with an outlook for high indium content channel MOSFETs. GaAs based MOSFETs are potentially suitable for RF power amplification, switching, and front-end integration in mobile and wireless applications while MOSFETs with high indium content channels are of interest for future CMOS applications.


Japanese Journal of Applied Physics | 2006

Low-Hydrogen-Content Silicon Nitride Deposited at Room Temperature by Inductively Coupled Plasma Deposition

H. Zhou; Khaled Elgaid; Chris D. W. Wilkinson; I.G. Thayne

A novel room-temperature inductively coupled plasma chemical vapour deposition (ICP–CVD) technique has been developed, which yielded high-quality silicon nitride (SiN) films with a hydrogen content of less than 3 at. %. The chemical composition and bonding of the films were analysed by energy dispersive X-ray (EDX) analysis, secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), and Fourier transform infrared spectroscopy (FTIR). The film optical indexes measured by ellipsometry were well correlated with film composition. Very little plasma-induced damage was observed on Van de Pauw samples of GaAs-based high-electron-mobility transistor (HEMT) layer structures grown by molecular beam epitaxy (MBE). Breakdown electric field >4×106 V cm-1 was observed for an ultrathin 5 nm room-temperature-grown ICP–CVD SiN film embedded in a metal-insulator-metal (MIM) capacitor structure. This technique has been successfully incorporated into the III–V MMIC process flow to provide significant flexibility towards realising array-based MMICs.


IEEE Electron Device Letters | 2011

Electron Mobility in Surface- and Buried-Channel Flatband

S. Bentley; M. Holland; Xu Li; G. W. Paterson; H. Zhou; Olesya Ignatova; D.S. Macintyre; S. Thoms; Asen Asenov; Byungha Shin; Jaesoo Ahn; Paul C. McIntyre; I.G. Thayne

In this letter, we investigate the scaling potential of flatband III-V MOSFETs by comparing the mobility of surface and buried-channel In<sub>0.53</sub>Ga<sub>0.47</sub>As devices employing an atomic layer-deposited Al<sub>2</sub>O<sub>3</sub> gate dielectric and a delta-doped InGaAs/InAlAs/InP heterostructure. Peak electron mobilities of 4300 cm<sup>2</sup>/V · s and 6600 cm<sup>2</sup>/V · s at a carrier density of 3 × 10<sup>12</sup> cm<sup>-2</sup> were determined for the surfaceand buried-channel structures, respectively. In contrast to similarly scaled inversion-channel devices, we find that the mobility in surface channel flatband structures does not drop rapidly with the electron density, but rather high mobility is maintained up to carrier concentrations around 4 × 10<sup>12</sup> cm<sup>-2</sup> before slowly dropping to around 2000 cm<sup>2</sup>/V · s at 1 × 10<sup>13</sup> cm<sup>-2</sup>. We believe these to be world leading metrics for this material system and an important development in informing the III-V MOSFET device architecture selection process for the future low-power highly scaled CMOS.


IEEE Electron Device Letters | 2012

\hbox{In}_{0.53}\hbox{Ga}_{0.47}\hbox{As}

R. Oxland; Shou-Zen Chang; Xu Li; S. W. Wang; G. Radhakrishnan; W. Priyantha; M.J.H. van Dal; Chih-Hua Hsieh; G. Vellianitis; G. Doornbos; K. Bhuwalka; B. Duriez; I.G. Thayne; R. Droopad; M. Passlack; Carlos H. Diaz; Y. C. Sun

We report an ultrashallow metallic source/drain (S/D) contact scheme for fully self-aligned III-V NMOS with specific contact resistivity and sheet resistance which, for the first time, demonstrate performance metrics that may be compatible with the ITRS R<sub>ext</sub> requirements for 12-nm technology generation device pitch. The record specific contact resistivity between the contact pad and metallic S/D of ρ<sub>c</sub> = 2.7 ·10<sup>-9</sup> Ω·cm<sup>2</sup> has been demonstrated for 10 nm undoped InAs channels by forming an ultrashallow crystalline ternary NiInAs phase with R<sub>sh</sub> = 97 Ω/sq for a junction depth of 7 nm. The junction depth of the S/D scheme is highly controllable and atomically abrupt.


IEEE Electron Device Letters | 2011

MOSFETs With ALD

S. Bentley; M. Holland; Xu Li; G. W. Paterson; H. Zhou; Olesya Ignatova; D.S. Macintyre; S. Thoms; A. Asenova; Byungha Shin; Jaesoo Ahn; Paul C. McIntyre; I.G. Thayne

In this letter, we investigate the scaling potential of flatband III-V MOSFETs by comparing the mobility of surface and buried-channel In<sub>0.53</sub>Ga<sub>0.47</sub>As devices employing an atomic layer-deposited Al<sub>2</sub>O<sub>3</sub> gate dielectric and a delta-doped InGaAs/InAlAs/InP heterostructure. Peak electron mobilities of 4300 cm<sup>2</sup>/V · s and 6600 cm<sup>2</sup>/V · s at a carrier density of 3 × 10<sup>12</sup> cm<sup>-2</sup> were determined for the surfaceand buried-channel structures, respectively. In contrast to similarly scaled inversion-channel devices, we find that the mobility in surface channel flatband structures does not drop rapidly with the electron density, but rather high mobility is maintained up to carrier concentrations around 4 × 10<sup>12</sup> cm<sup>-2</sup> before slowly dropping to around 2000 cm<sup>2</sup>/V · s at 1 × 10<sup>13</sup> cm<sup>-2</sup>. We believe these to be world leading metrics for this material system and an important development in informing the III-V MOSFET device architecture selection process for the future low-power highly scaled CMOS.


IEEE Transactions on Electron Devices | 2008

\hbox{Al}_{2}\hbox{O}_{3}

K. Kalna; Natalia Seoane; Antonio J. Garcia-Loureiro; I.G. Thayne; Asen Asenov

The potential performance of n-type implant-free (IF) III-V nanoMOSFETs with an In0.75Ga0.25As channel is studied using finite-element heterostructure Monte Carlo (MC) and parallel 3D drift-diffusion (D-D) simulations. These devices, scaled to gate lengths of 30, 20, and 15 nm, are compared with the equivalent gate length In0.3Ga0.7As channel IF MOSFETs and with a state-of-the-art Si TriGate FinFET. The benchmarking study is based on careful calibration of the MC simulator against experimental transport data obtained from relevant delta-doped heterostructures with a high-k gate dielectric. At 0.8-V supply voltage, the 30-nm gate length In0.75Ga0.25As channel IF III-V MOSFET is predicted to deliver a drive current of 2880 muA/mum and to have a subthreshold slope of 94.7 mV/dec compared with 2380 muA/mum for an equivalent gate length In0.3Ga0.7As channel IF MOSFET. When the In0.75Ga0.25As channel IF transistor is scaled to 20- and 15-nm gate lengths, the drive current increases to 3520 and 3605 muA/mum, featuring subthreshold slopes of 107.8 and 131.7 mV/dec, respectively. The threshold voltage variability induced by the discrete dopants in the delta-doped plane is studied using 3-D D-D simulations. The 30-, 20-, and 15-nm gate length In0.7Ga0.25As channel IF transistors exhibit threshold voltage standard deviations of 42, 58, and 61 mV, respectively, which are close to or lower than those observed in bulk Si MOSFETs with equivalent gate lengths.


IEEE Electron Device Letters | 2013

Gate Dielectric

Ata Khalid; Chong Li; V. Papageogiou; G M Dunn; M. J. Steer; I.G. Thayne; Martin Kuball; C. H. Oxley; M. Montes Bajo; A. Stephen; James Glover; David R. S. Cumming

We present the first results of a planar Gunn diode made in In<sub>0.53</sub>Ga<sub>0.47</sub>As on an InP substrate, operating at a fundamental frequency up to 164 GHz. For a 120-μm-wide device with a 1.3- μm active channel length, the highest power achieved was approximately -10 dBm at 164 GHz.

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Xu Li

University of Glasgow

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S. Thoms

University of Glasgow

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H. Zhou

University of Glasgow

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