Hi-Keung Tony Ma

MUSTANG: state assignment of finite state machines targeting multilevel logic implementations

The problem of state assignment for synchronous finite-state machines (FSM), targeted towards multilevel combinational logic and feedback register implementations, are addressed. The authors present state-assignment algorithms that heuristically maximize the number of common cubes in the encoded network to maximize the number of literals in the resulting combinational logic network after multilevel logic optimization. Results over a wide range of benchmarks which prove the efficacy of the proposed techniques are presented. Literal counts averaging 20%-40% less than other state-assignment programs have been obtained. >

Test generation for sequential circuits

An approach to test-pattern generation for synchronous sequential circuits is presented. The deterministic sequential test-generation algorithm, based on extensions to the PODEM justification algorithm, is effective for midsized sequential circuits and can be used in conjunction with an incomplete scan design approach to generate tests for very large sequential circuits. Tests for finite-state machines with a large number of states have been successfully generated using reasonable amounts of CPU time and close-to-maximum possible fault coverages have been obtained. For very large sequential circuits, an incomplete scan-design approach to test generation has been developed. The deterministic test generation algorithm is again used to generate test for faults in the modified circuit. All irredundant faults can be detected as in the complete scan design case, but at significantly less area and performance cost. The length of the test sequences for the faults can be bounded by a prescribed value-in general, a tradeoff exists between the number of memory elements required to be made scannable and the maximum allowed length of the test sequence. >

A synthesis and optimization procedure for fully and easily testable sequential machines

The authors outline a synthesis procedure which beginning from a state transition graph (STG) description of a sequential machine produces an optimized fully and easily testable logic implementation. This logic-level implementation is guaranteed to be testable for all single stuck-at faults in the combinational logic and the test sequences for these faults can be obtained using combinational test generation techniques alone. The sequential machine is assumed to have a reset state and be R-reachable. All single stuck-at faults in the combinational logic and the input and output stuck-at faults of the memory elements in the synthesized logic-level automaton can be tested without access to the memory elements using these test sequences. Thus this procedure represents an alternative to a scan design methodology. The area penalty incurred due to the constraints on the optimization are small. The performance of the synthesized design is usually better than that of an unconstrained design optimized for area alone. The authors show that an intimate relationship exists between state assignment and the testability of a sequential machine. They propose a procedure of constrained state assignment and logic optimization which guarantees testability for both Moore and Mealy machines. >

An incomplete scan design approach to test generation for sequential machines

An incomplete scan design approach to sequential test generation is presented. This approach represents a significant departure from previous methods. First, using an efficient sequential testing algorithm, test sequences are generated for a large number of possible faults in the given sequential circuit. A minimal subset of memory elements is then found, which if made observable and controllable will result in easy detection of the sequentially redundant and irredundant but difficult-to-defect faults. The deterministic test generation algorithm is again used to generate tests for these faults in the modified circuit (the circuit with the identified memory elements made scannable). Detection of all irredundant faults can be guaranteed as in the complete scan design case, but at significantly less area and performance cost.<<ETX>>

Logic Verification Algorithms and their Parallel Implementation

LOVER incorporates a novel approach to combinational logic verification and obtains good results when compared to existing techniques. In this paper we describe a new verification algorithm, LOVER-PODEM, whose enumeration phase is based on PODEM. A variant of LOVER-PODEM, called PLOVER, is presented. We have developed, for the first time, parallel logic verification schemes. Issues in efficiently parallelizing both general and specific LOVER-based approaches to logic verification over a large number of processors are addressed. We discuss parallelism inherent in the LOVER framework regardless of what enumeration and simulation algorithms are used. Since the enumeration phase is the efficiency bottleneck in parallelizing LOVER-based approaches, we have developed parallel versions of PODEM-based enumeration algorithms. Experimental results are presented to show that high processor utilization can be achieved when these parallelisms are exploited. Speed-up factors of over 7.8 have been achieved with 8 processor configurations.

Optimal logic synthesis and testability: two faces of the same coin

The relationships between test generation and logic minimization are described. An overview of the state of the art in combinational and sequential logic synthesis is provided. Combinational logic synthesis algorithms which can ensure irredundant and fully testable combinational circuits are reviewed. Test vectors which detect all single stuck-at faults in the combination logic can be obtained as a by-product of the logic minimization step. Equally intimate relationships between the problems of sequential logic synthesis and sequential test generation are envisioned. A recently developed synthesis technique of constrained state assignment and logic optimization which ensures fully testable sequential machines is described briefly.<<ETX>>

A practical and efficient method for compare-point matching

An important step in using combinational equivalence checkers to verify sequential designs is identifying and matching corresponding compare-points in the two sequential designs to be verified. Both non-function and function-based matching methods are usually employed in commercial verification tools. In this paper, we describe a heuristic algorithm using ATPG for matching compare-points based on the functionality of the combinational blocks in the sequential designs. Results on industrial-sized circuits show our methods are both practical and efficient.

Techniques for multilayer channel routing

The techniques described have been implemented in a multilayer channel router called Chameleon. Chameleon consists of two stages: a partitioner and a detailed router. The partitioner divides the problems into two-layer and three-layer subproblems such that global channel area is minimized. The detailed router then implements the connections using generalizations of the algorithms used in YACR2 (see ibid., vol.CAD-4, no.3, p.208-19, 1985). In particular, a three-dimensional maze router is used for the vertical connections; this methodology is effective even when cycle constraints are present. Chameleon has produced optimal results on a wide range of industrial and academic examples for a variety of layer and pitch combinations, and can handle a variety of technology constraints. >

A robust solution to the timing convergence problem in high-performance design

Traditional ASIC design flows have treated logic synthesis and physical design as separate steps in the flow. A recent trend in design automation has been to integrate placement and logic synthesis operations for designs that strive for high performance. The motivation for this is ascribed to achieving timing convergence. These efforts attempt a brute-force combination of techniques from the two fields. We present an architecture for combining synthesis transforms with rough placement. There are three main contributions of this paper. First we present a system architecture that permits a clean separation of placement and synthesis issues and combines the two solutions in an elegant manner. Second, we propose a minor modification to the current ASIC design flow to enable timing convergence. Third, we use design rules for correct circuit operation to drive the placement and the synthesis components of the system. We present results for a set of high performance ASIC designs which demonstrate the practicality of our method.

Logic verification algorithms and their parallel implementation

LOgic VERification (LOVER) incorporates a novel approach to combinational logic verification and obtains excellent results when compared to existing techniques. The authors describe a new verification algorithm, LOVER-PODEM, whose enumeration phase is based on PODEM. A variant of LOVER-PODEM, called PLOVER, is presented. Parallel logic verification schemes have been developed for the first time. Issues in efficiently parallelizing both general and specific LOVER-based approaches to logic verification over a large number of processors are addressed. The parallelism inherent in the LOVER framework regardless of what enumeration and simulation algorithms are used is discussed. Since the enumeration phase is the efficiency bottleneck in parallelizing LOVER-based approaches, parallel versions of PODEM-based enumeration algorithms have been developed. >