Donald O. Pederson

Macromodeling of integrated circuit operational amplifiers

A macromodel has been developed for integrated circuit (IC) op amps which provides an excellent pin-for-pin representation. The model elements are those which are common to most circuit simulators. The macromodel is a factor of more than six times less complex than the original circuit, and provides simulated circuit responses that have run times which are an order of magnitude faster and less costly in comparison to modeling the op amp at the electronic device level. Expressions for the values of the elements of the macromodel are developed starting from values of typical response characteristics of the op amp. Examples are given for three representative op amps. In addition, the performance of the macromodel in linear and nonlinear systems is presented. For comparison, the simulated circuit performance when modeling at the device level is also demonstrated.

Efficient transient simulation of lossy interconnect

The problem of transient simulation of lossy transmission lines is investigated in this paper. Two refinements are made to the existing convolution approach for the case of a single lossy line analytical formulae are derived for the line’s impulse-responses, and an accurate numerical convolution technique that utilises these formulae are devised. It is shown that a special case of lossy multiconductor lines can be decomposed into uncoupled lossy lines and linear memoryless networks, leading to a simple simulation algorithm. Simulation results on industrial circuits with single and mtdticonductor lossy lines are presented and compared with results obtained using lumped and pseudo-lumped approximations of lossy lines. The comparison indicates that the convolution technique with the above enhancements can be an order-ofmagnitude faster than lumped and pseudo-lumped segmenting techniques for equivalent or better accuracy.

Algorithms for the transient simulation of lossy interconnect

In this paper, a new linear-time technique is described for the simulation of lossy lines with frequency-independent R, L, C and G. Exact analytic forms are shown to exist for the frequency-independent lossy line, with application in both the new technique and the conventional convolution method. Numerical convolution formulae that exploit the analytic forms are presented. Experimental results for industrial circuits indicate that the new technique can be 10 and 50 times faster than the convolution and lumped-RLC methods, respectively, for long simulations. >

Coupling algorithms for mixed-level circuit and device simulation

A general framework for mixed-level circuit and device simulation is described. This framework was used in the development of the simulation program CODECS (coupled device and circuit simulator). Various algorithms to couple the device and circuit simulators for DC and transient analyses have been implemented in CODECS. These algorithms are evaluated based on their convergence properties and run-time performance. This study provides guidelines for choosing a particular coupling algorithm. A modified two-level Newton algorithm is used for DC analysis, whereas a full block-LU decomposition algorithm is used for transient analysis. This combination of algorithms provides reasonable convergence and run-time performance. A simple latency scheme provides a 50% speedup. Coupling for small-signal AC and pole-zero analyses are described. >

Elements of Computer-Aided Circuit Analysis

A survey is made of the principal techniques, procedures, and routines that are used in present programs for computeraided circuit analysis. Programs (simulators) are reviewed and selected features compared for the four major classes of circuit analysis: linear dc and ac, nonlinear dc, nonlinear transient, and linear pole zero.

Design aids for VLSI: The Berkeley perspective

Computer aids for integrated circuit (IC) design have been an integral part of the Berkeley IC program since its inception in the early 1960s. While our initial work concentrated on the development of simulation programs, such as SPICE2 and SPLICE, we are currently developing an integrated design system for VLSI circuits. The system is based on 1) the use of dedicated design stations, connected among themselves and to peripheral equipment via a high-speed computer network, and 2) a portable operating system framework for the integration of a set of design programs. This paper describes our ongoing research in the area of layout design and verification, simulation, synthesis, and optimization for VLSI design.

Design of Integrable Desensitized Frequency Selective Amplifiers

Synthesis procedures are presented for the synthesis of prototype frequency selective amplifiers suitable for semiconductor integrated circuit realization. Constraints and degrees of freedom imposed by semiconductor integrated passive and active components are incorporated in feedback amplifier designs. In order to achieve desensitized response, first-order pole-sensitivity functions are used in the synthesis. This leads to procedures for the simultaneous realization of prescribed response and response invariance. The procedures require feedback structures with redundant transmission-loops to provide extra degrees of freedom needed in the design. Experimental results from prototype amplifiers are presented.

CODECS: a fixed mixed-level device and circuit simulator

Mixed-level device and circuit simulation allows the use of one- or two-dimensional numerical models for critical devices in a circuit configuration. CODECS is a mixed-level device and circuit simulator that has been developed to support a variety of numerical models and analyses capabilities. Effective coupling of device and circuit simulation capabilities is achieved by a proper choice of algorithms and architecture. Several examples illustrate the advantages of CODECS for simulating both MOS and bipolar circuits.<<ETX>>

A New Design Approach for Feedback Amplifiers

A new design procedure is presented which is based on the root-locus technique. The realization of the following is possible: a) desired closed-loop response bandwidth (or rise time) and gain level (or amount of desensitivity); b) desired response shapes such as flat magnitude or flat delay; and c) desensitivity of both low-frequency and bandedge responses. The key feature of the root-locus technique is the proper use and location of phantom zeros (transmission zeros of the feedback path). To illustrate the technique, a shunt-shunt feedback configuration is used together with the realization of flat-magnitude-type closed-loop responses. The basic amplifier is a three-stage c-e transistor cascade. Typical design examples with experimental results are included.

An impulse-response based linear time-complexity algorithm for lossy interconnect simulation

A linear time-complexity algorithm for lossy transmission line simulation within arbitrary nonlinear circuits is presented. The method operates by storing information about the state of the line at dynamically selected internal points and using an analytical formulation based on impulse responses to predict the lines future behavior accurately. Previous approaches using impulse responses possess quadratic-time complexity. The proposed method does not require rational or other approximations of transfer functions to achieve linear time-complexity, nor does it increase the size of the simulators matrix by more than 2 for each transmission line. Experimental results on industrial circuits indicate that, for equivalent or superior accuracy, the state-based method can be faster for simulations of one or more block or data pulses, with speedups of more than 10 and 50 over the convolution and lumped-RLC methods for the longer simulations.<<ETX>>