A. Richard Newton

Logic synthesis for large pass transistor circuits

Pass transistor logic (PTL) can be a promising alternative to static CMOS for deep sub-micron design. In this work, we motivate the need for CAD algorithms for PTL circuit design and propose decomposed BDDs as a suitable logic level representation for synthesis of PTL networks. Decomposed BDDs can represent large, arbitrary functions as a multi-stage circuit and can exploit the natural, efficient mapping of a BDD to PTL. A comprehensive synthesis flow based on decomposed BDDs is outlined for PTL design. We show that the proposed approach allows us to make logic-level optimizations similar to the traditional multi- level network based synthesis flow for static CMOS, and also makes possible optimizations with a direct impact on area, delay and power of the final circuit implementation which do not have any equivalent in the traditional approach. We also present a set of heuristical algorithms to synthesize PTL circuits optimized for area, delay and power which are key to the proposed synthesis flow. Experimental results on ISCAS benchmark circuits show that our technique yields PTL circuits with substantial improvements over static CMOS designs. In addition, to the best of our knowledge this is the first time PTL circuits have been synthesized for the entire ISCAS benchmark set.

Sequential logic testing and verification

List of Figures.- List of Tables.- Preface.- Acknowledgements.- 1 Introduction.- 1.1 IC Design Systems.- 1.2 Implementation Verification.- 1.3 Testing.- 1.4 Synthesis For Testability.- 1.5 Outline.- 2 Sequential Test Generation.- 2.1 Preliminaries.- 2.2 Methods for Sequential Test Generation.- 2.2.1 Random Techniques.- 2.2.2 Deterministic Techniques.- 2.3 Test Generation Strategy.- 2.4 Cover Extraction and Combinational ATG.- 2.5 Justification.- 2.6 Initialization of Circuits.- 2.7 State Differentiation.- 2.8 Identification of Redundant Faults.- 2.9 Test Generation Results Using STEED.- 2.10 Conclusions.- 3 Test Generation Using RTL Descriptions.- 3.1 Preliminaries.- 3.2 Previous Work.- 3.3 Global Strategy for Test Generation.- 3.4 State Justification.- 3.5 Indexed Backtracking.- 3.6 Conflict Resolution.- 3.6.1 Assembling the equations.- 3.7 State Differentiation.- 3.8 Test Generation Results Using ELEKTRA.- 3.9 Conclusions.- 4 Sequential Synthesis for Testability.- 4.1 Preliminaries.- 4.1.1 Eliminating Sequential Redundancies.- 4.2 Previous Work.- 4.3 Theoretical Results.- 4.3.1 An Unconditional Testability Theorem.- 4.3.2 Logic Partitioning.- 4.4 The Synthesis and Test Strategy.- 4.5 Detection of Invalid States.- 4.6 Detection of Equivalent States.- 4.7 Experimental Results.- 4.8 Conclusions.- 5 Verification of Sequential Circuits.- 5.1 Preliminaries.- 5.2 Previous Work.- 5.3 Implicit STG Traversal.- 5.3.1 Incompletely-specified machines.- 5.4 Implicit STG Enumeration.- 5.4.1 Traversal versus enumeration.- 5.5 Experimental Results.- 5.6 Conclusions.- 6 Symbolic FSM Traversal Methods.- 6.1 Preliminaries.- 6.1.1 Binary Decision Diagrams.- 6.1.2 Sets and Characteristic Functions.- 6.2 Traversal by Recursive Range Computation.- 6.3 Traversal based on Transition Relations.- 6.3.1 Iterative Squaring.- 6.3.2 Detecting Equivalent States.- 6.4 Depth-First Geometric Chaining.- 6.4.1 An Autonomous Counter.- 6.4.2 A Loop Counter.- 6.5 A Mixed Traversal Algorithm.- 6.5.1 Introduction.- 6.5.2 k-Convergence and t-Periodicity.- 6.5.3 Traversing Cascaded Machines.- 6.5.4 Traversing Mutually Interacting Machines.- 6.5.5 Generalization to Multiple Submachines.- 6.5.6 Input-Selection-Based Traversal.- 6.6 Implementation of Algorithm.- 6.7 Experimental Results.- 6.8 Conclusions.- 7 Conclusions.- 7.1 Test Generation.- 7.2 Synthesis for Testability.- 7.3 Verification.- 7.4 Directions for Future Work.

Robust sketched symbol fragmentation using templates

Analysis of sketched digital ink is often aided by the division of stroke points into perceptually-salient fragments based on geometric features. Fragmentation has many applications in intelligent interfaces for digital ink capture and manipulation, as well as higher-level symbolic and structural analyses. It is our intuitive belief that the most robust fragmentations closely match a users natural perception of the ink, thus leading to more effective recognition and useful user feedback. We present two optimal fragmentation algorithms that fragment common geometries into a basis set of line segments and elliptical arcs. The first algorithm uses an explicit template in which the order and types of bases are specified. The other only requires the number of fragments of each basis type. For the set of symbols under test, both algorithms achieved 100% fragmentation accuracy rate for symbols with line bases, ›99% accuracy for symbols with elliptical bases, and ›90% accuracy for symbols with mixed line and elliptical bases.

EDA and the network

Digital computer networks are playing an increasingly important role in the evaluation, distribution, integration and management of EDA systems. Tools, libraries, design data, and a variety of both design and manufacturing services are accessible today via networks. Networks are also playing a central role in the integration of system design teams, teams that involve a variety of both business and technical disciplines as well as widely distributed geographical locations. Throughout the history of EDA, the architectures used to integrate and distribute computation and interaction have played a central role in the overall design methodology and so have had a major, indirect impact on the choice of the most effective tools, algorithms, and data structures. In this paper, a number of the factors involved in the choice of a suitable architecture for EDA integration are reviewed and a number of ongoing developments and challenges are presented.

The future of logic synthesis and physical design in deep-submicron process geometries

As device geometries shrink, a new set of challenges are faced by integrated circuit designers who use design automation tools. Existing software tools and methodologies must evolve to meet these challenges. Current design methodologies are stretched to the point where convergence on a final solution requires multiple iterations of the tool set. Most problems can be attributed to assumptions about technology made by tools and the methodology that are no longer valid. It is clear that a major change in design methodology is required. In this paper, we examine current design methodology and explore avenues to face the deep-submicron challenge.

Retargetable estimation scheme for DSP architecture selection

Given the recent wave of innovation and diversification in digital signal processor (DSP) architecture, the need for quickly evaluating the true potential of considered architectural choices for a given application has been rising. We propose a new scheme, called retargetable estimation, that involves analysis of a high-level description of a DSP application, with aggressive optimization search, to provide a performance estimate of its optimal implementation on the architectures considered. With this scheme, we present a new parameterized architecture model that allows quick retargeting to a wide range of architectural choices, and that emphasizes capturing an architectures salient optimizing features. We show that for a set of DSP benchmarks and two full applications, hand-optimized performance can be predicted reliably. We applied this scheme to two different processors.

An estimation technique to guide low power resynthesis algorithms

Existing resynthesis procedures used for reducing power consumption in CMOS networks have produced poor results as they select nodes for resynthesis based upon local circuit properties. In this paper, a technique is presented for optimizing the choice of regions used in resynthesis. The cost function which is developed is able to predict the amount of global improvement in power expected through the resynthesis of network nodes under both zero as well as arbitrary delay assumptions. A series of empirical tests have been completed which demonstrate the need for a global approach to the estimation of optimality. The tests results demonstrate that there are often a significant number of nodes which are highly non-optimal in a global sense which would not usually be selected for resynthesis using existing techniques. The estimator predicts these cases with a high degree of accuracy.

TOBAC: a test case browser for testing object-oriented software

TOBAC1 is part of a test management system for object-oriented software. A test case browser built under the Smalltalk-80 environment to dejire, manage and execute test cases is introduced. The main benejit of TOBA C is support for regression testing of complex objects. TOBAC is selfadaptable to the structure of an arbitrary complex object.

Predicting performance potential of modern DSPs

High-level development tools for digital signal processors (DSPs) remain unable to extract optimal performance from them without the designers in-depth knowledge of the architecture. In this paper we describe our approach to Retargetable Estimation and show how and why it can be effective in quickly predicting and guiding toward hand-optimized performance of moderns DSPs for a given application described in a high-level language. We also contrast the advantages of this scheme with those of a full-featured optimizing compiler.

Integration of retiming with architectural floorplanning

The concept of improving the timing behavior of a circuit by relocating registers is called retiming and was first presented by Leiserson and Saxe. They showed that the problem of determining an equivalent minimum area (total number of registers) circuit is polynomial-time solvable. In this work, we show how this approach can be reapplied in the deep sub-micron domain when area-delay trade-offs and delay constraints are considered. The main result is that the concavity of the trade-off function allows for casting this problem into a classical minimum area retiming problem. The solution paves the way for retiming to be incorporated in the architectural floorplanning stage of a design flow tailored for deep sub-micron circuits. Some examples and a register-based interconnect strategy suitable to the developed retiming technique on global wires is presented.