Premal Buch

Logic synthesis for large pass transistor circuits

Pass transistor logic (PTL) can be a promising alternative to static CMOS for deep sub-micron design. In this work, we motivate the need for CAD algorithms for PTL circuit design and propose decomposed BDDs as a suitable logic level representation for synthesis of PTL networks. Decomposed BDDs can represent large, arbitrary functions as a multi-stage circuit and can exploit the natural, efficient mapping of a BDD to PTL. A comprehensive synthesis flow based on decomposed BDDs is outlined for PTL design. We show that the proposed approach allows us to make logic-level optimizations similar to the traditional multi- level network based synthesis flow for static CMOS, and also makes possible optimizations with a direct impact on area, delay and power of the final circuit implementation which do not have any equivalent in the traditional approach. We also present a set of heuristical algorithms to synthesize PTL circuits optimized for area, delay and power which are key to the proposed synthesis flow. Experimental results on ISCAS benchmark circuits show that our technique yields PTL circuits with substantial improvements over static CMOS designs. In addition, to the best of our knowledge this is the first time PTL circuits have been synthesized for the entire ISCAS benchmark set.

Techniques for fast circuit simulation applied to power estimation of CMOS circuits

We present a transistor level power estimator which exploits algorithms for fast circuit simulation to compute the power dissipation of CMOS circuits. The proposed approach uses stepwise equivalent conductance and piecewise linear waveform approximation. The power estimator has been implemented in the SWEC framework. Experimental results indicate that SWEC can obtain a substantial speed-up over HSPICE while maintaining an accuracy of within 5-7%. Benchmark results on a suite of industry circuits, which include circuits that HSPICE could not handle, are presented.

SYMPHONY: a fast mixed signal simulator for BiMOS analog/digital circuits

SYMPHONY a mixed signal simulator which exploits the special characteristics of BiMOS mixed signal circuits is presented. SYMPHONY contains a fast simulator for digital circuits and several new techniques to efficiently simulate BiMOS circuits. The typical switching behavior of bipolar devices in digital setting is exploited by using a simplified model to approximate the bipolar device characteristics. The problem of minimizing the worst case approximation error is formulated and a heuristic is proposed to achieve this by using a PWL model with expanded Chebyshev points as the breakpoints. Dynamic circuit partitioning is combined with an event-driven approach to exploit the latency and multi-rate behavior. Experimental results demonstrate that SYMPHONY can yield 2/spl times/-250/spl times/ speed-up over SPICE3e depending upon the amount of analog circuitry present in the design.

A parallel graph partitioner on a distributed memory multiprocessor

In order to realize the full potential of speed-up by parallelization, it is essential to partition a problem into small tasks with minimal interactions without making this process itself a bottleneck. We present a method for graph partitioning that is suitable for parallel implementation and scales well with the number of processors and the problem size. Our algorithm uses hierarchical partitioning. It exploits the parallel resources to minimize the dependence on the starting point with multiple starts at the higher levels of the hierarchy. These decrease at the lower levels as it zeroes in on the final partitioning. This is followed by a last-gasp phase that randomly collapses partitions and repartitions to further improve the quality of the fmat solution. Each individual 2-way partitioning step can be performed by any standard partitioning algorithm. Results are presented on a set of benchmarks representing connectivity graphs of device and circuit simulation problems.<<ETX>>