A. S. Mandal

Area Optimized FPGA-Based Implementation of The Sobel Compass Edge Detector

This paper presents a new FPGA resource optimized hardware architecture for real-time edge detection using the Sobel compass operator. The architecture uses a single processing element to compute the gradient for all directions. This greatly economizes on the FPGA resources usages (more than 40% reduction) while maintaining real-time video frame rates. The measured performance of the architecture is 50u2009fps for standard PAL size video and 200u2009fps for CIF size video. The use of pipelining further improved the performance (185u2009fps for PAL size video and 740u2009fps for CIF size video) without significant increase in FPGA resources.

Design of an application specific instruction set processor for parametric speech synthesis

Parametric speech synthesizers utilize digital parameterized source-filter models for modeling the process of production of human speech. They are used in speech synthesis systems with an unlimited vocabulary. Presently, they are available as C language codes that run on PC platforms. They require a moderately high throughput of a mix of floating-point DSP functions and non-DSP (general-purpose) type computations. For embedded unlimited vocabulary speech synthesis systems, therefore, a need has been felt for the design of an Application Specific Integrated Processor for parametric speech synthesis. The present work describes the design of an Application Specific Instruction Set Processor (ASIP) for parametric speech synthesis that can serve the needs of embedded speech synthesis systems.

Application Specific Instruction Set Processors: redefining hardware-software boundary

Logic functions have many different architectural alternatives for their implementations. These range from dedicated combinational and sequential architectures to different types of programmable CPU architectures. Each architectural alternative presents a unique set of advantages and limitations. The choice of an architecture is decided based on how well the speed-power-cost and design time trade-offs that the architectures offers matches the designs requirement. While both the dedicated hardware architectures and the software architectures (programmable CPU based) have a long history of research and exploration, it is comparatively more recently that one has started seeing the trend of leveraging the best features of both these kinds of architectures via designing new programmable architectures, namely the Application Specific Instruction Set Processor (ASIP) architectures. The idea of present paper is to discuss the comparative benefits and limitations of both the dedicated hardware architectures and the software based general purpose architectures and identify how the benefit of these architectures can be realized through a single architecture-the ASIP architecture.

Design of a fast and efficient hardware implementation of a random number generator in FPGA

This research paper presents a fast and efficient hardware implementation of a pseudo-random number generator based on Lehmer linear congruential method. We demonstrate in this paper that how the introduction of application specificity in the architecture can deliver huge performance in terms of area and speed. The design has been specified in VHDL and is implemented on Xilinx FPGA device XC5VFX130T-3ff1738 and takes up only 23 slice LUTS. Our design generates 1 random number per cycle with a clock frequency of 502 MHz (502 million samples per second). The random numbers generated by our design are extensively verified against the C-code generated outputs for functional correctness.

Real-Time Implementation of Change Detection for Automated Video Surveillance System

Change detection is one of the several important problems in the design of any automated video surveillance system. Appropriate selection of frames of significant changes can minimize the communication and processing overheads for such systems. This research presents the design of a VLSI architecture for change detection in a video sequence and its implementation on Virtex-IIPro FPGA platform. Clustering-based scheme is used for change detection. The proposed system is designed to meet the real-time requirements of video surveillance applications. It robustly detects the changes in a video stream in real time at 25 frames per second (fps) in gray scale CIF size video.

Hardware accelerator design for tracking in smart camera

Smart Cameras are important components in video analysis. For video analysis, smart cameras needs to detect interesting moving objects, track such objects from frame to frame, and perform analysis of object track in real time. Therefore, the use of real-time tracking is prominent in smart cameras. The software implementation of tracking algorithm on a general purpose processor (like PowerPC) could achieve low frame rate far from real-time requirements. This paper presents the SIMD approach based hardware accelerator designed for real-time tracking of objects in a scene. The system is designed and simulated using VHDL and implemented on Xilinx XUP Virtex-IIPro FPGA. Resulted frame rate is 30 frames per second for 250x200 resolution video in gray scale.

Hardware accelerator design for change detection in smart camera

Smart Cameras are important components in Human Computer Interaction. In any remote surveillance scenario, smart cameras have to take intelligent decisions to select frames of significant changes to minimize communication and processing overhead. Among many of the algorithms for change detection, one based on clustering based scheme was proposed for smart camera systems. However, such an algorithm could achieve low frame rate far from real-time requirements on a general purpose processors (like PowerPC) available on FPGAs. This paper proposes the hardware accelerator capable of detecting real time changes in a scene, which uses clustering based change detection scheme. The system is designed and simulated using VHDL and implemented on Xilinx XUP Virtex-IIPro FPGA board. Resulted frame rate is 30 frames per second for QVGA resolution in gray scale.

Memory Efficient VLSI Implementation of Real-Time Motion Detection System Using FPGA Platform

Motion detection is the heart of a potentially complex automated video surveillance system, intended to be used as a standalone system. Therefore, in addition to being accurate and robust, a successful motion detection technique must also be economical in the use of computational resources on selected FPGA development platform. This is because many other complex algorithms of an automated video surveillance system also run on the same platform. Keeping this key requirement as main focus, a memory efficient VLSI architecture for real-time motion detection and its implementation on FPGA platform is presented in this paper. This is accomplished by proposing a new memory efficient motion detection scheme and designing its VLSI architecture. The complete real-time motion detection system using the proposed memory efficient architecture along with proper input/output interfaces is implemented on Xilinx ML510 (Virtex-5 FX130T) FPGA development platform and is capable of operating at 154.55 MHz clock frequency. Memory requirement of the proposed architecture is reduced by 41% compared to the standard clustering based motion detection architecture. The new memory efficient system robustly and automatically detects motion in real-world scenarios (both for the static backgrounds and the pseudo-stationary backgrounds) in real-time for standard PAL (720 × 576) size color video.

Embedded Implementation of Change Detection Algorithm for Smart Camera Applications

Smart cameras are important components in any Human Computer Interaction. In any remote surveillance scenario, smart cameras have to take intelligent decisions to select frames of interest to minimize communication and processing overhead. A clustering based change detection algorithm has been implemented in our smart camera system for filtering frames with significant changes. In this paper we propose a platform based framework for implementing clustering based change detection algorithm using HW-SW co-design based methodology. The complete system is implemented on Xilinx XUP Virtex-II Pro FPGA board. The overall algorithm is running on PowerPC405 and some of the blocks which are computationally intensive and more frequently called are implemented as custom IP using VHDL. Total gate count of the design is 2699K.

Evolution of architectural concepts and design methods of microprocessors

Microprocessors constitute one of the most important classes of VLSI chips. Over the last 25 years their architectures and capabilities have evolved rapidly to pack enormous computing power in them. However, this has made the task of designing successive generations of microprocessors increasingly complex. Methodologies used to design microprocessors have also accordingly changed from generation to generation. The purpose of this paper is to summarize these evolutions in architecture and design methodologies of microprocessors and present a microprocessors design example using a methodology that makes efficient use of the HDL-based design approach to create portable microprocessor designs for use in system-level integrated products.