Anil K Saini

A novel real-time resource efficient implementation of Sobel operator-based edge detection on FPGA

A new resource efficient FPGA-based hardware architecture for real-time edge detection using Sobel operator for video surveillance applications has been proposed. The choice of Sobel operator is due to its property to counteract the noise sensitivity of the simple gradient operator. FPGA is chosen for this implementation due to its flexibility to provide the possibility to perform algorithmic changes in later stage of the system development and its capability to provide real-time performance, hard to achieve with general purpose processor or digital signal processor, while limiting the extensive design work, time and cost required for application specific integrated circuit. The proposed architecture uses single processing element for both horizontal and vertical gradient computation for Sobel operator and utilised approximately 38% less FPGA resources as compared to standard Sobel edge detection architecture while maintaining real-time frame rates for high definition videos (1920 × 1080 image sizes). The complete system is implemented on Xilinx ML510 (Virtex-5 FX130T) FPGA board.

Comprehensive Review and Comparative Analysis of Hardware Architectures for Sobel Edge Detector

This paper presents a comprehensive review and a comparative study of various hardware/FPGA implementations of Sobel edge detector and explored different architectures for Sobel gradient computation unit in order to show the various trade-offs involved in choosing one over another. The different architectures using pipelining and/or parallelism (key methodologies for improving the performance/frame rates) are explored for gradient computation unit in Sobel edge detector. How the different architectures affected performance (in terms of video frame rate and image size) and area (in terms of FPGA resources usages) has been demonstrated. By exploiting the trade-offs between video frame rate, image size, and FPGA resources a designer should be able to find an optimal architecture for a given application.

A self biased operational amplifier at ultra low power supply voltage

This paper discusses the design of a self-biased folded cascode operational amplifier at an ultra low power supply voltage. The proposed design is first of its kind at 0.5 V where self-biasing techniques are used to reduce power and area overheads. The self-biasing scheme in this design is developed by using a current mirror for low voltage operation. This design is implemented in a 90 nm CMOS technology using Cadence General Purpose Design Kit (GPDK).

Design of a fast and efficient hardware implementation of a random number generator in FPGA

This research paper presents a fast and efficient hardware implementation of a pseudo-random number generator based on Lehmer linear congruential method. We demonstrate in this paper that how the introduction of application specificity in the architecture can deliver huge performance in terms of area and speed. The design has been specified in VHDL and is implemented on Xilinx FPGA device XC5VFX130T-3ff1738 and takes up only 23 slice LUTS. Our design generates 1 random number per cycle with a clock frequency of 502 MHz (502 million samples per second). The random numbers generated by our design are extensively verified against the C-code generated outputs for functional correctness.

DC Offset Modeling and Noise Minimization for Differential Amplifier in Subthreshold Operation

This work presents the rigorous formulation of input referred offset voltage for differential amplifier, having the input pair devices in subthreshold region of operation. The formulation has been verified in 0.35 μm and 0.18 μm CMOS technologies by using Monte Carlo Simulation. Minimization of 1/f noise is the additional advantage of this method.

Analyzing impact of image scaling algorithms on viola-jones face detection framework

In todays world of automation, real time face detection with high performance is becoming necessary for a wide number of computer vision and image processing applications. Existing software based system for face detection uses the state of the art Viola and Jones face detection framework. This detector makes use of image scaling approach to detect faces of different dimensions and thus, performance of image scalar plays an important role in enhancing the accuracy of this detector. A low quality image scaling algorithm results in loss of features which directly affects the performance of the detector. Therefore, in this paper we have analyzed the effect of different image scaling algorithms existing in literature on the performance of the Viola and Jones face detection framework and have tried to find out the optimal algorithm significant in performance. The algorithms which will be analyzed are: Nearest Neighbor, Bilinear, Bicubic, Extended Linear and Piece-wise Extended Linear. All these algorithms have been integrated with the Viola and Jones face detection code available with OpenCV library and has been tested with different well know databases containing frontal faces.

An FPGA implementation of image signature based visual-saliency detection

In this paper we present a prototype FPGA design for Saliency detection based on image signature technique to support embedded vision application. Visual attention supports biological vision to restrict our gaze only to the region of interest of a visual scene. We propose a pipelined architecture using Gaussian filter, Discrete Cosine Transform, Inverse Discrete Cosine Transform and Averaging block that is shared across the system. The investigation involves simulation and synthesis of VHDL code using ModelSimTM and Xilinx Synthesis Toolbox as design environments. Due to real-time requirements and computational-cost constraints in embedded systems, it is necessary to accelerate Saliency detection algorithm by hardware implementation. Experiment shows that the proposed hardware has the maximum clock speed of 160 MHz with Xilinx ML510 (Virtex-5 FX130T) FPGA platform.

Hardware Accelerator for Facial Expression Classification Using Linear SVM

In this paper, we present hardware accelerator for Facial Expression Classification using One-Versus-All (OVA) linear Support Vector Machine (SVM) classifier. The motivation behind this work is to perform real-time classification of facial expressions into three different classes: neutral, happy and pain, which could be used in an embedded system to facilitate automatic patient monitoring in ICUs of hospitals without any personal assistance. Pipelining and parallelism (inherent qualities of FPGAs) have been utilized in our architecture to achieve optimal performance. For achieving high accuracy, the architecture has been designed using IEEE-754 single precision floating-point data format. We performed the SVM training offline and used the trained parameters to implement its testing part on Field Programmable Gate Array (FPGA). Synthesis result shows that the designed architecture is operating at a maximum clock frequency of 200 MHz. Classification accuracy of 97.87% has been achieved on simulating the design with different test images. Thus, the designed architecture of the OVA linear SVM shows good performance in terms of both speed and accuracy facilitating real-time classification of the facial expressions.

Analyzing hardware constraints of Gabor filtering operation for Facial Expression Recognition System

This paper presents hardware constraints analysis of Gabor filtering operation for its hardware implementation in a real time Facial Expression Recognition System (FERS). Gabor filter is the most common feature extractor employed for the realization of such system. Feature extraction using Gabor filter is efficient and has better discrimination capability. In this work, we have employed software-based approach to find the optimum filter and facial image size. These two factors employed in the Gabor filtering process directly affect the hardware resource utilization and hence we have considered these two factors for our analysis. We have used two versions of Gabor filter for feature extraction, one using the original Gabor filtering approach and the other its modified version using Image Pyramid based approach. Support Vector Machine (SVM) classifier has been used for analyzing the performance of the extracted feature.

VLSI architecture of Pairwise Linear SVM for facial expression recognition

In this paper, we present VLSI architecture of Pairwise Linear Support Vector Machine (SVM) classifier for multi-classification on FPGA. The objective of this work is to facilitate real time classification of the facial expressions into three categories: neutral, happy and pain, which could be used in a typical patient monitoring system. Thus, the challenge here is to achieve good performance without compromising the accuracy of the classifier. In order to achieve good performance pipelining and parallelism (key methodologies for improving the performance/frame rates) have been utilized in our architectures. We have used pairwise SVM classifier because of its greater accuracy and architectural simplicity. The architectures has been designed using fixed-point data format. Training phase of the SVM is performed offline, and the extracted parameters have been used to implement testing phase of the SVM on the hardware. According to simulation results, maximum frequency of 241.55 MHz, and classification accuracy of 97.87% has been achieved, which shows a good performance of our proposed architecture.