Pramod Tanwar

Design of an application specific instruction set processor for parametric speech synthesis

Parametric speech synthesizers utilize digital parameterized source-filter models for modeling the process of production of human speech. They are used in speech synthesis systems with an unlimited vocabulary. Presently, they are available as C language codes that run on PC platforms. They require a moderately high throughput of a mix of floating-point DSP functions and non-DSP (general-purpose) type computations. For embedded unlimited vocabulary speech synthesis systems, therefore, a need has been felt for the design of an Application Specific Integrated Processor for parametric speech synthesis. The present work describes the design of an Application Specific Instruction Set Processor (ASIP) for parametric speech synthesis that can serve the needs of embedded speech synthesis systems.

Application Specific Instruction Set Processors: redefining hardware-software boundary

Logic functions have many different architectural alternatives for their implementations. These range from dedicated combinational and sequential architectures to different types of programmable CPU architectures. Each architectural alternative presents a unique set of advantages and limitations. The choice of an architecture is decided based on how well the speed-power-cost and design time trade-offs that the architectures offers matches the designs requirement. While both the dedicated hardware architectures and the software architectures (programmable CPU based) have a long history of research and exploration, it is comparatively more recently that one has started seeing the trend of leveraging the best features of both these kinds of architectures via designing new programmable architectures, namely the Application Specific Instruction Set Processor (ASIP) architectures. The idea of present paper is to discuss the comparative benefits and limitations of both the dedicated hardware architectures and the software based general purpose architectures and identify how the benefit of these architectures can be realized through a single architecture-the ASIP architecture.

Implementation of Dynamically Reconfigurable Systems on Chip with OS Support

This work presents the implementation of dynamically reconfigurable system with operating system support specifically Linux. The presented work combines both HW and SW flows where the complex parts of the architecture are designed to HW modules. These HW modules can be reconfigured on the fly by using partial dynamic reconfiguration. In our work, we are using floating point computation unit as partial reconfiguration module. Our aim is to show the idea how an operating system can be involved in the area of reconfiguration computing. The application that manages the reconfiguration can be developed either as standalone software that is specific for the system or with an operating system support, to achieve code reusability and code portability. Finally, a prototype is implemented on Xilinx ML507 board, where a general Linux open source kernel has been used to handle dynamic reconfigurable hardware recourses.

Implementation of Real Time Graphical User Interface Library for Dynamic Reconfigurable System

This work presents the implementation of real time GUI library for FPGA based run time reconfigurable system that is targeted to ML507 board. The presented work implements floating point arithmetic core as a reconfigurable IP and operands can be provide to the above core with GUI running on display monitor. User can interact with GUI with keyboard and mouse. GUI allows user to change the functionality of the circuit in run time by clicking on appropriate buttons. This approach combines both HW and SW flows. The HW module can be reconfigured on the fly by using partial dynamic reconfiguration.

Wireless sensor networks based public addressing system

This paper explains the idea of using wireless sensor networks based system for public addressing system. In this paper, we describe how to transmit audio without wires using a simple concept of wireless sensor network. Though wireless sensor networks are meant for transmitting low-data rate, in our work we extended it to transmit audio. In this work, we have considered Jennic JN5139R1 micro-controller for the implementation system. Jennic micro-controller ported with contiki OS with μIP protocol of IPv6 and UDP service libraries. Novelty of this work is using all open source tools to develop the public addressing system. The work carried out here is transmitting and receiving audio data between two wireless nodes that are interfaced serially with PC.

Multi obstacle identification using image processing technique

Robotics technology has come out so far that it has necessitated the need of robots in almost every field. Machine vision is an identified field of research contributing to the success of robotic technology. Workspace cleaning robot extends this to yet another application of robotics with machine vision primarily focusing on obstacle detection and avoidance. This paper is an attempt to detect multiple objects, by tracing their outer boundaries by extending an already existing Moore Neighbor tracing method. The logic is successful in detecting the outer boundaries and is further needed for implementing the cellular decomposition of Boustrophedon algorithm which can be used for covering whole area.

Implementation of Dynamic Reconfigurable Audio Player and Spectrum Analyzer

This work presents the implementation of FPGA based run time reconfigurable audio player system that is targeted to ML507 board with frequency component display of the stored audio data. The presented work combines both HW and SW flows where the complex parts of the architecture are designed to HW modules. These HW modules can be reconfigured on the fly by using partial dynamic reconfiguration. In our work, we are using filter block as partial reconfiguration module, 16 point FFT to decimate audio sample data in frequency in SW logic and displaying the spectrum of the audio signal on the display monitor. Our aim is to implement reconfigurable complex audio player as an application of reconfiguration computing, proving how this technique may be helpful to decrease resource utilization of the device with negligible performance overhead.

High Frame Rate Real-Time Scene Change Detection System

Scene change detection, one of the fundamental and most important problem of computer vision, plays a very important role in the realization of a complete industrial vision system as well as automated video surveillance system - for automatic scene analysis, monitoring, and generation of alerts based on relevant changes in a video stream. Therefore, in addition to being accurate and robust, a successful scene change detection system must also be of very high frame rate in order to detect scene changes which goes off within a glimpse of the eye and often goes unnoticeable by the conventional frame rate cameras. Keeping the high frame rate processing as main focus, a very high frame rate real-time scene change detection system is developed by leveraging VLSI design to achieve high performance. This is accomplished by proposing, designing, and implementing an area-efficient scene change detection VLSI architecture on FPGA-based IDP Express platform. The developed prototype of complete real-time scene change detection system is capable of processing 2000 frames per second for 512 × 512 video resolution and is tested for live incoming video streams from high speed camera. The proposed and implemented system architecture is adaptable and scalable for different video resolutions and frame rates.

Improved method of image segmentation and feature extraction for embedded fingerprint identification system

An improved method of fingerprint image segmentation and feature extraction has been proposed for the efficient implementation of Automated Fingerprint Identification System (AFIS) on embedded platform. Fingerprint image is segmented based upon the local mean and local variance of the image to reduce the computation. Spatial domain Gabor filter is used for the image enhancement and features are extracted from thinned binary fingerprint image using the crossing number. Entire algorithm is implemented on ARM processor development platform with WindowsCE6.0 operating system.