Ravi Saini

A novel real-time resource efficient implementation of Sobel operator-based edge detection on FPGA

A new resource efficient FPGA-based hardware architecture for real-time edge detection using Sobel operator for video surveillance applications has been proposed. The choice of Sobel operator is due to its property to counteract the noise sensitivity of the simple gradient operator. FPGA is chosen for this implementation due to its flexibility to provide the possibility to perform algorithmic changes in later stage of the system development and its capability to provide real-time performance, hard to achieve with general purpose processor or digital signal processor, while limiting the extensive design work, time and cost required for application specific integrated circuit. The proposed architecture uses single processing element for both horizontal and vertical gradient computation for Sobel operator and utilised approximately 38% less FPGA resources as compared to standard Sobel edge detection architecture while maintaining real-time frame rates for high definition videos (1920 × 1080 image sizes). The complete system is implemented on Xilinx ML510 (Virtex-5 FX130T) FPGA board.

Design of an application specific instruction set processor for parametric speech synthesis

Parametric speech synthesizers utilize digital parameterized source-filter models for modeling the process of production of human speech. They are used in speech synthesis systems with an unlimited vocabulary. Presently, they are available as C language codes that run on PC platforms. They require a moderately high throughput of a mix of floating-point DSP functions and non-DSP (general-purpose) type computations. For embedded unlimited vocabulary speech synthesis systems, therefore, a need has been felt for the design of an Application Specific Integrated Processor for parametric speech synthesis. The present work describes the design of an Application Specific Instruction Set Processor (ASIP) for parametric speech synthesis that can serve the needs of embedded speech synthesis systems.

Application Specific Instruction Set Processors: redefining hardware-software boundary

Logic functions have many different architectural alternatives for their implementations. These range from dedicated combinational and sequential architectures to different types of programmable CPU architectures. Each architectural alternative presents a unique set of advantages and limitations. The choice of an architecture is decided based on how well the speed-power-cost and design time trade-offs that the architectures offers matches the designs requirement. While both the dedicated hardware architectures and the software architectures (programmable CPU based) have a long history of research and exploration, it is comparatively more recently that one has started seeing the trend of leveraging the best features of both these kinds of architectures via designing new programmable architectures, namely the Application Specific Instruction Set Processor (ASIP) architectures. The idea of present paper is to discuss the comparative benefits and limitations of both the dedicated hardware architectures and the software based general purpose architectures and identify how the benefit of these architectures can be realized through a single architecture-the ASIP architecture.

Comprehensive Review and Comparative Analysis of Hardware Architectures for Sobel Edge Detector

This paper presents a comprehensive review and a comparative study of various hardware/FPGA implementations of Sobel edge detector and explored different architectures for Sobel gradient computation unit in order to show the various trade-offs involved in choosing one over another. The different architectures using pipelining and/or parallelism (key methodologies for improving the performance/frame rates) are explored for gradient computation unit in Sobel edge detector. How the different architectures affected performance (in terms of video frame rate and image size) and area (in terms of FPGA resources usages) has been demonstrated. By exploiting the trade-offs between video frame rate, image size, and FPGA resources a designer should be able to find an optimal architecture for a given application.

Design of a fast and efficient hardware implementation of a random number generator in FPGA

This research paper presents a fast and efficient hardware implementation of a pseudo-random number generator based on Lehmer linear congruential method. We demonstrate in this paper that how the introduction of application specificity in the architecture can deliver huge performance in terms of area and speed. The design has been specified in VHDL and is implemented on Xilinx FPGA device XC5VFX130T-3ff1738 and takes up only 23 slice LUTS. Our design generates 1 random number per cycle with a clock frequency of 502 MHz (502 million samples per second). The random numbers generated by our design are extensively verified against the C-code generated outputs for functional correctness.

Analyzing impact of image scaling algorithms on viola-jones face detection framework

In todays world of automation, real time face detection with high performance is becoming necessary for a wide number of computer vision and image processing applications. Existing software based system for face detection uses the state of the art Viola and Jones face detection framework. This detector makes use of image scaling approach to detect faces of different dimensions and thus, performance of image scalar plays an important role in enhancing the accuracy of this detector. A low quality image scaling algorithm results in loss of features which directly affects the performance of the detector. Therefore, in this paper we have analyzed the effect of different image scaling algorithms existing in literature on the performance of the Viola and Jones face detection framework and have tried to find out the optimal algorithm significant in performance. The algorithms which will be analyzed are: Nearest Neighbor, Bilinear, Bicubic, Extended Linear and Piece-wise Extended Linear. All these algorithms have been integrated with the Viola and Jones face detection code available with OpenCV library and has been tested with different well know databases containing frontal faces.

An FPGA implementation of image signature based visual-saliency detection

In this paper we present a prototype FPGA design for Saliency detection based on image signature technique to support embedded vision application. Visual attention supports biological vision to restrict our gaze only to the region of interest of a visual scene. We propose a pipelined architecture using Gaussian filter, Discrete Cosine Transform, Inverse Discrete Cosine Transform and Averaging block that is shared across the system. The investigation involves simulation and synthesis of VHDL code using ModelSimTM and Xilinx Synthesis Toolbox as design environments. Due to real-time requirements and computational-cost constraints in embedded systems, it is necessary to accelerate Saliency detection algorithm by hardware implementation. Experiment shows that the proposed hardware has the maximum clock speed of 160 MHz with Xilinx ML510 (Virtex-5 FX130T) FPGA platform.

Hardware accelerator design for tracking in smart camera

Smart Cameras are important components in video analysis. For video analysis, smart cameras needs to detect interesting moving objects, track such objects from frame to frame, and perform analysis of object track in real time. Therefore, the use of real-time tracking is prominent in smart cameras. The software implementation of tracking algorithm on a general purpose processor (like PowerPC) could achieve low frame rate far from real-time requirements. This paper presents the SIMD approach based hardware accelerator designed for real-time tracking of objects in a scene. The system is designed and simulated using VHDL and implemented on Xilinx XUP Virtex-IIPro FPGA. Resulted frame rate is 30 frames per second for 250x200 resolution video in gray scale.

Hardware accelerator design for change detection in smart camera

Smart Cameras are important components in Human Computer Interaction. In any remote surveillance scenario, smart cameras have to take intelligent decisions to select frames of significant changes to minimize communication and processing overhead. Among many of the algorithms for change detection, one based on clustering based scheme was proposed for smart camera systems. However, such an algorithm could achieve low frame rate far from real-time requirements on a general purpose processors (like PowerPC) available on FPGAs. This paper proposes the hardware accelerator capable of detecting real time changes in a scene, which uses clustering based change detection scheme. The system is designed and simulated using VHDL and implemented on Xilinx XUP Virtex-IIPro FPGA board. Resulted frame rate is 30 frames per second for QVGA resolution in gray scale.

Hardware Accelerator for Facial Expression Classification Using Linear SVM

In this paper, we present hardware accelerator for Facial Expression Classification using One-Versus-All (OVA) linear Support Vector Machine (SVM) classifier. The motivation behind this work is to perform real-time classification of facial expressions into three different classes: neutral, happy and pain, which could be used in an embedded system to facilitate automatic patient monitoring in ICUs of hospitals without any personal assistance. Pipelining and parallelism (inherent qualities of FPGAs) have been utilized in our architecture to achieve optimal performance. For achieving high accuracy, the architecture has been designed using IEEE-754 single precision floating-point data format. We performed the SVM training offline and used the trained parameters to implement its testing part on Field Programmable Gate Array (FPGA). Synthesis result shows that the designed architecture is operating at a maximum clock frequency of 200 MHz. Classification accuracy of 97.87% has been achieved on simulating the design with different test images. Thus, the designed architecture of the OVA linear SVM shows good performance in terms of both speed and accuracy facilitating real-time classification of the facial expressions.