Aminghasem Safarian

Power Harvester Design for Passive UHF RFID Tag Using a Voltage Boosting Technique

This paper presents a guideline to design and optimize a power harvester circuit for an RF identification transponder. A power harvester has been designed and fabricated in a CMOS 0.18- process that operates at the UHF band of 920 MHz. The circuit employs an impedance transformation circuit to boost the input RF signal that leads to the improvement of the circuit performance. The power harvester has been optimized to achieve maximum sensitivity by characterizing both the impedance transformation network and the rectifier circuit and choosing the optimum values for the circuit parameters. The measurement results show sensitivity of 14.1 dBm for dc output voltage of 1 V and the output current of 2 mum that corresponds to the output power of 2 muW.

A UHF Near-Field RFID System With Fully Integrated Transponder

This paper presents an RF identification (RFID) system with a fully integrated transponder. To enable the on-chip integration of the tags antenna, it is suggested to employ near-field coupling at high-frequency ranges, i.e., the UHF band. The RFID system including the reader and key blocks of the transponder is designed and fabricated in a standard CMOS 0.18-mum process. The system operates at 900 MHz with the coverage range of over 0.4 cm. The tags antenna is integrated on-chip without using any special process. The reader employs multiple coils to increase its coverage area. Using a proper output network, the reader can deliver a current of 225 mA (rms) to its coil, which is designed on a printed circuit board.

CMOS Distributed Active Power Combiners and Splitters for Multi-Antenna UWB Beamforming Transceivers

This paper presents the design of the first CMOS distributed active power combiners and splitters with wideband variable delay and gain. These circuits are the key components for use in multi-antenna (MA) ultra-wideband (UWB) point-to-point beamforming communication systems with multiple transmit and receive antennas. Two broadband circuit topologies for each active power combiner and splitter are proposed, one of which being fabricated in a 0.13-mum CMOS process. The proposed fabricated distributed active power combiner and splitter operate across wide range of frequencies that cover the UWB frequency range from 3.1 to 10.6 GHz. The gain of each RF path of the power combiner and splitter is independently controllable from -15 to 6 dB and from -16 to 9.5 dB, respectively. The wideband variable delay of each RF path varies from 32 to 42 ps for the two-stage power combiner, and from 43 to 53 ps for the three-stage power splitter across the UWB frequency range. Supplied from 1.8-V DC voltage, the power combiner and splitter consume 8.5 mA and 11.4 mA, respectively.

A Two-Point Modulation Technique for CMOS Power Amplifier in Polar Transmitter Architecture

A two-point modulation technique is presented that improves the performance of nonlinear power amplifiers (PAs) in polar transmitters. In this scheme, the output amplitude modulation is performed by controlling the current of the PA. The current control technique enables the PA to provide wideband amplitude modulation, as well as high power control dynamic range. In addition, the supply voltage of the PA is adjusted based on the output power level. The voltage supply adjustment substantially improves the effective power efficiency of the PA. The voltage supply control is performed using a second-order sigma-delta dc-dc converter, which presents an efficiency of over 95% in its operational range. The PA operates at 900 MHz with maximum output power of 27.8 dBm and power efficiency of 34% at maximum output power. The proposed PA achieves 62-dB power control dynamic range with amplitude modulation bandwidth of over 17.1 MHz. The circuits are fabricated in a CMOS 0.18 mum process with a 3.3-V power supply.

RF Identification (RFID) Reader Front Ends With Active Blocker Rejection

This paper presents a novel active blocker rejecting RF (ABR-RF) front end for RF identification (RFID) applications. The proposed ABR-RF injects the blocker replica within the low-noise amplifier of the RFID receiver chain, through a feed-forward path to actively create an arbitrary narrowband notch filtering for the in-band blockers, while not affecting the gain of the desired signal. The in-band blocker is from the leakage of the RFID self-transmitter because RFID systems use backscattering communication. The notch frequency of the ABR-RF is always locked to the RFID transmitter frequency without any passive element tuning. Fabricated in a 0.18- mum CMOS technology, the prototype improves the ABR-RFs 1-dB compression point by greater than 18 dB, and achieves a 50-dB signal-to-blocker ratio improvement. The receiver path draws 40 mA from a 1.8-V supply voltage. The blocker filtering path adds maximum of 16 mA to reject a maximum in-band blocker of 20 dBm. The die area is 1.8 times 1.2 mm2.

A Distributed RF Front-End for UWB Receivers

This paper presents the design and fabrication of a novel silicon-based distributed RF front-end for ultra wideband (UWB) receivers (RX). The proposed UWB distributed RF front-end, called UWB-DRF, is suitable for UWB IF transceiver architectures. The circuit constitutes of combined low-noise amplifier (LNA) and down-conversion mixer cells distributed along the artificial transmission lines (TLs), to achieve wideband conversion gain, noise figure (NF), and linearity. A 3 stage UWB-DRF was fabricated in a 0.13 mum CMOS process. The prototype UWB-DRF achieves 13.8-15.5 dB gain over the entire UWB frequency range, while exhibiting flat NF of 5.2 dB across the band. The radio-frequency (RF), local-oscillator (LO), and intermediate-frequency (IF) ports are wideband-matched to 50Q. A programmable RF termination allows the UWB-DRF to achieve higher gain of 17.7 dB and lower NF of 3.5 dB, while trading off with few decibels of mismatch at the RF input port

An Integrated RFID Reader

A UHF RFID reader that handles RFID tag information as weak as -80dBm along with large inband blockers as large as 20dBm is presented. Fabricated in a 0.18mum CMOS process, the reader selectively attenuates large inband blockers, 40 to 250kHz away from the tag information, by better than 30dB using the limiting concept, while amplifying the tag information by 18dB.

Distributed Active Power Combiners and Splitters for Multi-Antenna UWB Transceivers

This paper presents the design of CMOS active power combiners and splitters with wideband variable gain and delay using distributed architectures. The proposed circuits are the key components for use in multi-antenna (MA) ultra-wideband (UWB) communication systems with beamforming. The proposed distributed active power combiner and splitter operate across 1-10.6GHz bandwidth. Power gain of each path of the combiner and splitter is independently controllable from -15dB to 6dB and from -16dB to 9.5dB, respectively. The wideband variable delay of each path of the power combiner is 32 to 42 ps, and for each path of the power splitter is 43 to 53 ps across the UWB frequency range. Both power combiner and splitter have been fabricated in a 0.13mum CMOS process. Supplied from a 1.8V power-supply, the 2-stage distributed active power combiner consumes 8.5mA, and the 3-stage distributed active power splitter draws 11.4mA

On the Dynamics of Regenerative Frequency Dividers

A comprehensive analytical study of regenerative frequency dividers (RFD) is presented. The study includes two fundamental modes of operation in RFDs, namely locked (or stable) and quasi-locked modes, and the study also covers the transition from free-running oscillation to quasi-locked, and ultimately to locked operation mode. Differential equations characterizing the RFD behavior for both operation modes as well as the transition between the two are derived. An RFD circuit for Bluetooth applications was designed and fabricated in a 65-nm CMOS process with a supply voltage of 1.2 V. Measurement results of the RFD prototype verify the accuracy of the proposed analytical models

An RFID System with Fully Integrated Transponder

This paper presents an RFID system with fully integrated transponder. The transmit path of the reader as well as key blocks of the tag is designed and fabricated in standard CMOS 0.18 mum process. The system operates at 900 MHz with the coverage range of more than 0.4 cm. The tags antenna is integrated on chip without using any special process. The reader employs a coil switching technique to increase its coverage area. The PA in the transmit path of the reader is designed using digital to RF configuration. By employing a proper output network, the PA can deliver a current of 225 mA (RMS) to the readers coil.