A. Tomar

Design of 1.1 GHz Highly Linear Digitally-Controlled Ring Oscillator with Wide Tuning Range

This paper presents a simple architecture for 8-bit digital controlled oscillator (DCO) on 3-stages ring topology in TSMC 0.35 mum CMOS technology. A new schematic of tristate inverter is also proposed. The proposed tristate inverter has higher switching speed and low power consumption as compared to conventional one. The control digit changes the driving current that provides large tuning range from 333 MHz to 1472 MHz with very good linearity. The output voltage swing is constant and above 3 volt (>90% of the supply voltage i.e. 3.3 V). The presented circuit shows the fast response to the output frequency transition and this takes less than one clock period and without showing any ringing or damping during frequency transition. The proposed DCO has simulated phase noise of -106 dBc/Hz @ 1 Mhz and 63.4 mw power consumption at 1.1 GHz central frequency.

Low phase noise 18 kHz frequency tuning step 5 GHz DCO using tiny capacitors based on transmissi on lines

We proposed a method to realize the fine frequency-tuning step using tiny capacitors instead of MIM capacitors for a digitally controlled oscillator (DCO). The tiny capacitors are realized by the coplanar transmission lines in a 6 metal layers (M6) foundry of 0.18 um CMOS technology. These transmission line based capacitors are designed by using electro-magnetic field simulator, and co-designed by using SPICE simulator. Finally, we fabricated the proposed DCO in 0.18 um CMOS technology, and tested. The measured phase noise of DCO was −118.3 dBc/Hz (@1MHz offset frequency), and the oscillating frequency tuned from 4.86 GHz to 5.36 GHz in the minimum frequency-tuning step of 18 kHz.

A wide tuning range −163 FOM CMOS quadrature ring oscillator for inductorless reconfigurable PLL

This paper presents the design and implementation of a quadrature voltage-controlled ring oscillator with the improved figure of merit (FOM) using the four single-ended inverter topology. A new topology to prevent the latch-up in single ended ring oscillators is proposed. The design is implemented in 0.18 µm CMOS technology and the measurement results show a FOM of −163.8 dBc/Hz with the phase noise of −125.8 dBc/Hz at 4 MHz offset from the carrier frequency of 3.62 GHz. It exhibits a frequency tuning range from 1.23 GHz to 4.17 GHz with coarse and fine frequency sensitivity of 1.08 MHz/mV and 120 kHz/mV, respectively.

Design of Highly Linear, 1GHz 8-bit Digitally Controlled Ring Oscillator with Wide Tuning Range in 0.18um CMOS Process

This paper presents a simple architecture for 8-bit digital controlled oscillator (DCO) on 3-stages ring topology in TSMC 0.18 um CMOS technology. A new schematic of tristate inverter is also proposed. The proposed tristate inverter has higher switching speed and low power consumption as compared to conventional one. The control digit changes the driving current that provides large tuning range from 316 MHz to 1165 MHz with very good linearity. The output voltage swing is always greater than 1.6 V while the supply voltage is 1.8 V. The proposed DCO has simulated phase noise of -114 dBc/Hz @1 MHz and 23.2 mW power consumption at 1.0 GHz central frequency.

Low phase noise 10 bit 5 GHz DCO using on-chip CPW resonator in 0.18 µm CMOS technology

A digital-controlled oscillator (DCO) employing on-chip coplanar waveguide (CPW) resonator is proposed for 5 GHz-band wireless communication applications. A 10 bit DCO using on-chip designed, fabricated and tested. By comparing the measured results on the fabricated chip in 0.18 µm CMOS technology, it has noted that the proposed DCO employing on-chip CPW resonator is smaller in size and frequency-tuning range is higher than LC-DCO. Phase noise and power consumption are comparable.

10 bit 2/5GHz dual band digitally-controlled LC-oscillator in 0.18 um CMOS Process

This paper presents a design methodology and verification of a 2/5 GHz dual band digitally-controlled oscillator (DCO). The presented DCO employed two spiral inductors and a switching transistor between them to operate at two bands of frequency. The switch is controlled by a digital signal so that shifting from one band of frequency to another to control the operation of spiral inductors needs no analog voltage signal. The proposed circuit is implemented in 0.18 um CMOS technology and tested. The measured phase noise was −120.5 dBc/Hz and −113.9 dBc/Hz (both @ 1 MHz offset) at carrier frequency of 2.7 GHz and 4.1 GHz, respectively.