Awinash Anand

Low Group Delay 3.1–10.6 GHz CMOS Power Amplifier for UWB Applications

This letter proposes the design of a low group delay ultra-wideband (UWB) power amplifier (PA) in CMOS technology. The PA design employs a three-stage cascade common source topology that has a different design concept from other multi-stage topology to provide a broad bandwidth characteristic, gain flatness of , and low group delay variation of . A resistive shunt feedback technique is adopted at the first stage of the amplifier to achieve good input matching, which controls the upper frequency of the UWB system. The third stage realizes the gain at the lower corner frequency and the second stage is used to smooth the flatness of the gain curve. By using this method, the proposed design has the lowest group delay variation among the recently reported CMOS PAs for 3.1 to 10.6 GHz applications.

Digitally controlled CMOS quadrature ring oscillator with improved FoM for GHz range all-digital phase-locked loop applications

This paper presents a 14-bit digitally controlled ring oscillator (DCO) with operating frequency up to 3.4 GHz in 0.18 µm CMOS technology. Digital control is employed to control the transistor operation to obtain higher voltage swing and lower flicker (1/f) noise that in turn results in the lowest phase noise in a ring oscillator. Furthermore, sub-feedback topology is used to obtain the stable quadrature outputs from even number of stages. The DCO has a frequency tuning from 523 MHz to 3.405 GHz. Phase noise at 4 MHz offset is −134.82 dBc/Hz. This results in figure of merit (FoM) to be −169.9 dBc/Hz which is 7.7 dB improvement over its recently published analog counterpart.

A third order delta-sigma modulator employing shared opamp technique for WCDMA on 0.18um CMOS

Analog to digital converter is a vital component in a wireless transceiver. High order loop filter is one of conventional approach to attain high resolution delta-sigma modulator which required one opamp for each integrator. A third orders delta-sigma modulator (DSM) has been designed utilizing shared opamp technique to reduce number of opamp required and decrease power consumption. Moreover, this architecture has relaxed comparator speed which is appropriate for wireless applications. First and second stages are sharing one opamp in integration and sampling phase. The proposed circuit has been designed on TSMC 0.18um CMOS technology. 2MHz Bandwidth, 50dB Peak SQNR, which is suitable for WCDMA, have been achieved.

An eight-phase CMOS injection locked ring oscillator with low phase noise

This paper presents the design of a low DC power, low phase noise single-ended ring oscillator (RO) in 0.18 μm CMOS technology. It introduces a new RO output phase control technique. This RO uses a voltage pull-down circuit to produce different output signal phases. The proposed RO employs the pulse injection (PI) technique for phase noise and spurious signals suppression. The proposed injection locked ring oscillator (ILRO) can be used for phase shift keying (PSK) implementation. The proposed ILRO has an oscillation frequency of 4.5 GHz with a fine tuning range of 540 MHz. It consumes only a 4.25 mW of power while having a phase noise of -130.9 dBc/Hz @ 1MHz offset. Through this ILRO design, a figure of merit (FoM) of -197.68 dBc/Hz has been achieved.

Systematic Design Methodology of a Wideband Multibit Continuous-Time Delta-Sigma Modulator

Systematic design of a low power, wideband and multi-bit continuous-time delta-sigma modulator (CTDSM) is presented. The design methodology is illustrated with a 640 MS/s, 20 MHz signal bandwidth 4th order 2-bit CTDMS implemented in 0.18 µm CMOS technology. The implemented design achieves a peak SNDR of 65.7 dB and a high dynamic range of 70 dB while consuming only 19.7 mW from 1.8 V supply. The design achieves a FoM of 0.31 pJ/conv. Direct path compensation is employed for one clock excess loop delay compensation. In the feedforward topology, capacitive summation using the last opamp eliminates extra summation opamp.

Feedforward charge injection technique in a continuous time delta-sigma modulator

In this paper, we analyze the feedforward charge injection technique (FCIT) in a continuous time delta-sigma modulator (CTDSM) and explain the theory behind improvement of SNR. We find that the feedforward charge injection technique (FCIT) in a CTDSM significantly reduces the node voltage swing at the input of the operational transconductance amplifier (OTA) and thereby relaxes the design constraint on OTA by suppressing third harmonics and thus reduces power consumption significantly. We also observe that there exist three different regions of design with respect to the power consumption out of which only one region is critical with respect to power reduction and robust design. Combined with the regions of design FCIT enables to design robust CTDSM with low power consumption.

Analytical method to determine optimal out-of-band gain in multi-bit delta-sigma modulator

A simple, systematic and deterministic MATLAB simulation which employs Risbo method and analytical simulation is proposed to determine the optimal out-of-band gain to achieve a maximal SNR and the maximum stable amplitude in a multi-bit delta-sigma modulator. Using the proposed method, a 128 MS/s, 2 MHz signal bandwidth 4th order 2-bit continuous-time delta-sigma modulator is designed and implemented in 0.18μm CMOS technology to verify the concept. As a result, the modulator achieves a peak SNDR of 79.3 dB and a dynamic range of 83 dB for a 2 MHz signal bandwidth (OSR = 32) while consuming only 7.8 mW from 1.8 V supply.

A novel 14-bit digitally controlled ring oscillator

A novel 14-bit digitally controlled ring oscillator is designed in 0.18 μm CMOS technology. Sub-feedback technique is used to increase the output frequency that produces stable oscillation with even number of stages. Frequency can be tuned from 674 MHz to 4 GHz. Phase noise at 4 GHz carrier frequency and 4 MHz offset is -119.4dBc/Hz. Figure of Merit (FoM) calculated is 156 dBc/Hz.