A. Wakabayashi

Two-dimensional analysis of substrate-trap effects on turn-on characteristics in GaAs MESFETs

Effects of substrate traps on turn-on characteristics of GaAs MESFETs are studied by two dimensional (2-D) simulation. When the off-state gate voltage is much more negative than the threshold (pinch off) voltage and the surface-state effects are small, abnormal current overshoot and subsequent slow transients are observed for the case with undoped semi-insulating substrate including an electron trap: EL2. Even if the surface-state effects are pronounced to show the large gate-lag, the drain current may show the overshoot-like behavior at relatively early periods. The case of Cr-doped substrate with a hole trap: Cr is also discussed.

Analysis of gate-lag phenomena in recessed-gate and buried-gate GaAs MESFETs

Two-dimensional analysis of gate-lag phenomena in recessed-gate and buried-gate GaAs MESFETs is performed, and their dependence on the structural parameters and the off-state gate voltage V/sub Goff/ is studied. It is shown that when V/sub Goff/ is around the threshold voltage (pinchoff voltage) V/sub th/, the gate-lag could be almost eliminated by introducing the buried-gate structure. However, it is suggested that large gate-lag might be seen when V/sub Goff/ is much more negative than V/sub th/.

Analysis of surface-state effects on gate-lag phenomena in recessed-gate and buried-gate GaAs MESFETs

Gate-lag or slow current transient behaviour in GaAs MESFETs is studied by two-dimensional analysis including surface-state effects. It is shown that in a recessed-gate structure, the gate-lag is reduced to some extent by increasing the recess depth, but it may not be suppressed as much as expected because surface states around the gate affect the turn-on characteristics. However, by introducing the buried-gate structure where the gate electrode is attached to the vertical planes of the recess and also to the same planes as the drain electrode, the surface-state effects are minimized, and the gate-lag can be greatly reduced.

Analysis of surface and substrate deep-trap effects on gate-lag phenomena in GaAs MESFETs

The gate-lag in GaAs MESFETs is a phenomenon that the drain current shows slow transient when the gate voltage is changed abruptly. This is a serious problem in both digital and analog GaAs ICs, but its mechanism is not well clarified. The surface states are thought to be main causes of this phenomenon, and device structures which can reduce surface-state effects, such as a self-aligned structure and a recessed-gate structure, are adopted. But the gate-lag sometimes arises even in these structures. So, in this work, we have studied the gate-lag phenomena in these device structures by two-dimensional numerical simulation, and found that the gate-lag may not be completely suppressed in the recessed-gate structure. In addition, we have simulated the substrate deep-trap effects, and found that abnormal transient can arise when the off-state gate voltage is deeply negative.

Physical mechanisms of performance instabilities such as gate-lag and kink phenomena in GaAs MESFETs

Slow current transients during turn-on (gate-lag) and abnormal increases in drain conductance (kink) in GaAs MESFETs are studied by two-dimensional analysis including surface states and impact ionization of carriers. Particularly, it is discussed how the gate-lag is influenced by impact ionization of carriers and how the surface-related kink depends on the structural parameters such as gate length and distance between source and gate.

Effects of surface deep levels on breakdown characteristics of narrowly-recessed-gate GaAs MESFETs

Effects of surface deep levels on breakdown characteristics of nnrrowly-recessedgate GaAs MESFETs are studied by two-dimensional analysis. I t is shown that the breakdown voltage could be raised when moderate densities of surface states are included. However, it is suggested that in n case with relatively high densifies of surface states, the breakdown vollage could be drastically lowered by introducing a narrowly-Tecess=d-g=te structure.

Numerical Modeling of Impact-Ionization Effects on Gate-Lag Phenomena in Gaas Mesfets

Two-dimensional simulation of turn-on characteristics of GaAs MESFETs is performed in which surface states and impact ionization of carriers are considered. It is shown that the gate-lag (or the slow current transient) becomes weaker when including the impact ionization. This is attributed to the fact that the potential profiles along the surface is drastically changed when the surface states capture holes that are generated by impact ionization. The relation between the gate-lag and the so-called kink phenomenon is also discussed.

Simulation of Drastic Lag Phenomena in GaAs-Based FETs for Large Voltage Swing

Turn-on characteristics of GaAs MESFETs and HEMTs are simulated when the gate voltage is changed abruptly. The gate-lag or slow current transient becomes more pronounced when the off-state gate voltage is more negative, because the surface-state effects or substrate-trap effects become more significant. Changes of I–V curves of GaAs MESFETs, when the drain voltage is swept with different speeds, are also simulated. When the swept time is short, the curve shows overshoot-like behavior and the kink disappears, indicating that the I–V characteristics should be quite different between DC and RF conditions.

Simulation of drastic lag phenomena in GaAs-based FETs for large voltage swing

In GaAs MESFETs and HEMTs, slow current transients are often observed experimentally even if the drain voltage or the gate voltage is changed abruptly. They are called drain-lag or gate-lag and could be fatal when the high-speed and high-frequency operation is considered. As for factors of these slow transients, effects of deep traps in the semi-insulating substrate and surface states on the active layer are suggested, but the detailed mechanisms are not well clarified. In this work, we have made transient simulations of GaAs MESFETs and AlGaAs/GaAs HEMTs when the gate voltage or the drain voltage is swung significantly, and showed that the lag phenomena become very pronounced for larger changes of the voltages. This indicates that I-V characteristics should be quite different between DC and RF conditions and the lag phenomena should be considered in the modeling of GaAs-based power devices.