K. Horio

Computer-aided analysis of GaAs n-i-n structures with a heavily compensated i-layer

Current-voltage characteristics and space-charge distributions in an n-i-n structure have been numerically analyzed and compared with Lamperts theory. It is found that an effective resistivity in the low-voltage region depends on acceptor and trap densities and the length of an i-layer. The analytical model has been presented to estimate the effective resistivity and the onset voltage for current rise. The back-gating effect also has been analyzed in terms of a separation distance between devices and an acceptor density. To achieve a good isolation between two devices in GaAs ICs, it is suggested that a shallow acceptor density as well as a trap density must be larger than a critical value.

Two-dimensional analysis of substrate-trap effects on turn-on characteristics in GaAs MESFETs

Effects of substrate traps on turn-on characteristics of GaAs MESFETs are studied by two dimensional (2-D) simulation. When the off-state gate voltage is much more negative than the threshold (pinch off) voltage and the surface-state effects are small, abnormal current overshoot and subsequent slow transients are observed for the case with undoped semi-insulating substrate including an electron trap: EL2. Even if the surface-state effects are pronounced to show the large gate-lag, the drain current may show the overshoot-like behavior at relatively early periods. The case of Cr-doped substrate with a hole trap: Cr is also discussed.

Physics-based simulation of buffer-trapping effects on slow current transients and current collapse in GaN field effect transistors

Two-dimensional transient analyses of GaN metal-semiconductor field effect transistors (MESFETs) are performed in which a three level compensation model is adopted for a semi-insulating buffer layer, where a shallow donor, a deep donor, and a deep acceptor are included. Quasipulsed current-voltage (I‐V) curves are derived from the transient characteristics and are compared with steady-state I‐V curves. It is shown that when the drain voltage VD is raised abruptly, the drain current ID overshoots the steady-state value, and when VD is lowered abruptly, ID remains at a low value for some periods, showing drain-lag behavior. These are explained by the deep donor’s electron capturing and electron emission processes quantitatively. The drain lag could be a major cause of current collapse, although some gate lag is also seen due to the buffer layer. The current collapse is shown to be more pronounced when the deep-acceptor density in the buffer layer is higher and when an off-state drain voltage is higher, beca...

Numerical simulation of GaAs MESFET's on the semi-insulting substrate compensated by deep traps

Numerical simulations of GaAs MESFETs are performed in which impurity compensation by deep traps in the semi-insulting substrate is considered. It is found that the higher acceptor density in the substrate results in lower device current due to the formation of a space-charge layer at the channel-substrate interface. It is also found that the drain currents increase continuously with the drain voltage because electrons are injected to fill the traps in the substrate and a current path through the substrate is formed. This substrate current becomes remarkable for shorter gate-length MESFETs on a substrate with lower acceptor and trap densities. It is suggested that, to minimize short-channel effects in GaAs MESFETs, the acceptor density as well as the trap density in the semi-insulating substrate must be high. >

Numerical simulation of AlGaAs/GaAs heterojunction bipolar transistors with various collector parameters

Numerical simulations of AlGaAs/GaAs HBTs (heterojunction bipolar transistors) with various collector parameters are carried out to investigate the cutoff frequency characteristics, using the conventional static model and the energy transport model. It is shown that the transit time in the collector depletion layer is an intrinsically more important factor than the collector charging time. Therefore, a thinner n/sup -/-layer with higher doping density is desirable to achieve higher cutoff frequency, f/sub T/. It is found that the importance of energy transport effects arises from the fact that the actual electron energy deviates strongly from the field determined energy. The velocity overshoot can occur in a graded bandgap base and in the collector depletion layer, resulting in much higher f/sub T/ than that predicted by the conventional model. A value of F/sub T/ higher than 140 GHz is expected for an HBT with an n/sup -/-layer thickness of 1000 AA. >

Numerical analysis of slow current transients and power compression in GaAs FETs

Two-dimensional transient simulation of GaAs MESFETs is performed when the gate voltage and the drain voltage are both changed abruptly. Quasi-pulsed current-voltage (I-V) curves are derived from the transient characteristics. It is discussed how the slow current transients (lag phenomena) and the pulsed I-V curves are affected by the existence of substrate traps and surface states. It is shown that the so-called power compression could occur both due to substrate traps and due to surface states. Effects of impact ionization of carriers on these phenomena are also discussed. It is shown that the lag phenomena and the power compression are weakened when impact ionization of carriers becomes important, because generated holes may help the traps to change their ionized densities quickly.

Physical Mechanism of Buffer-Related Current Transients and Current Slump in AlGaN/GaN High Electron Mobility Transistors

Two-dimensional transient analyses of AlGaN/GaN high electron mobility transistors (HEMTs) are performed in which a deep donor and a deep acceptor are considered in a buffer layer. Quasi-pulsed current–voltage (I–V) curves are derived from the transient characteristics. When the drain voltage is raised abruptly, electrons are injected into the buffer layer and captured by deep donors, and when it is lowered abruptly, the drain currents remain at low values for some periods and begin to increase slowly as the deep donors begin to emit electrons, showing drain-lag behavior. The gate lag could also occur due to deep levels in the buffer layer, and it is correlated with relatively high source access resistance in AlGaN/GaN HEMTs. It is shown that the current slump is more pronounced when the deep-acceptor density in the buffer layer is higher and when an off-state drain voltage is higher, because the trapping effects become more significant. The drain lag could be a major cause of current slump in the case of higher off-state drain voltage. It is suggested that to minimize current slump in AlGaN/GaN HEMTs, an acceptor density in the buffer layer should be made low, although there may be a trade-off relationship between reducing current slump and obtaining sharp current cutoff.

Two-dimensional simulation of GaAs MESFETs with deep acceptors in the semi-insulating substrate

Abstract Numerical simulations of GaAs MESFETs with deep chromium acceptors in the semi-insulating substrate were made. The results were compared with those obtained for a case with deep donors such as EL2 centers and shallow acceptors. It was found that an acceptor density in the substrate is a predominant factor in determining current-voltage characteristics of GaAs MESFETs, whether the acceptor is deep or shallow. Potential profiles were, however, found to depend strongly on the nature of deep levels in the substrate, suggesting that different drain breakdown characteristics or different backgating effects may be observed between the two cases. To minimize short-channel effects in GaAs MESFETs, the substrate conduction must be reduced. For this purpose, the deep-acceptor density in the semi-insulating substrate should be made high.

Analysis of field-plate effects on buffer-related lag phenomena and current collapse in GaN MESFETs and AlGaN/GaN HEMTs

A two-dimensional transient analysis of field-plate GaN MESFETs and AlGaN/GaN HEMTs is performed in which a deep donor and a deep acceptor are considered in a semi-insulating buffer layer, and quasi-pulsed current–voltage curves are derived from them. How the existence of a field plate affects buffer-related drain lag, gate lag and current collapse is studied. It is shown that in both MESFET and HEMT, the drain lag is reduced by introducing a field plate because electron injection into the buffer layer is weakened by it, and the buffer-trapping effects are reduced. It is also shown that the field plate could reduce buffer-related current collapse and gate lag in the FETs. The dependence of lag phenomena and current collapse on the field-plate length and on the SiN passivation layer thickness is also studied. The work suggests that in the field-plate structures, there is an optimum thickness of the SiN layer to minimize the buffer-related current collapse and drain lag in GaN MESFETs and AlGaN/GaN HEMTs.

Analysis of surface-state and impact-ionization effects on breakdown characteristics and gate-lag phenomena in narrowly recessed gate GaAs FETs

Effects of surface states and recess structures on breakdown characteristics of GaAs MESFETs are studied by two-dimensional (2-D) analysis. It is shown that the breakdown voltage could be raised when moderate densities of surface states are included. However, in a case with relatively high densities of surface states, the breakdown voltage could be drastically lowered when introducing a narrowly recessed gate structure. Effects of impact ionization on gate-lag phenomena in GaAs MESFETs are also studied. It is shown that the gate-lag becomes weaker when including the impact ionization. This is attributed to the fact that the potential profiles along the surface are drastically changed when the surface states capture generated carriers. It is suggested that there is a tradeoff relationship between raising the breakdown voltage and reducing the gate-lag.