A. Zaleski

In depth analysis of opposite channel based charge injection in SOI MOSFETs and related defect creation and annihilation

Abstract Extensive PISCES simulations, incorporating non-local effects are carried out to obtain an in-depth understanding of the recently observed opposite channel based charge injection in SOI MOSFETs [1]. This charge injection is then combined with basic transistor characteristics and charge pumping current measurements to study the hot carrier degradation mechanisms in a variety of SOI MOSFETs, and clarify the separate roles played by hot electrons and holes in the degradation. It is also used as the basis for the design of a new, SOI based flash memory cell.

Investigation of carrier generation in fully depleted enhancement and accumulation mode SOI MOSFET's

An unified dual gate Zerbst-like technique has been developed to extract the generation lifetime in enhancement and accumulation mode fully depleted SOI MOSFETs. The technique is based on the analysis of the temporal variation of the quasi Fermi levels in the devices, following the application of a suitable voltage step on one of the gates. The analysis resulted in simple Zerbst-like expressions for the drain current transients. Numerical simulations, using PISCES, have been performed to validate the technique and its underlying analysis. The technique has been applied to both kinds of typical fully depleted SIMOX SOI MOSFETs and the measured generation lifetimes were in the range of 0.1 /spl mu/s to 1.0 /spl mu/s. >

Successive charging/discharging of gate oxides in SOI MOSFET's by sequential hot-electron stressing of front/back channel

Hot-hole injection into the opposite channel of silicon-on-insulator (SOI) MOSFETs under hot-electron stress is reported. Sequential front/back-channel hot-electron stressing results in successive hot-electron/-hole injection, causing the threshold voltage to increase and decrease accordingly. This ability to inject hot holes into the opposite gate oxide can be used as an additional tool for studying the degradation mechanisms. Furthermore, it can be explored for possible use in designing SOI flash memory cells with back-channel-based erasing schemes.<<ETX>>

Opposite-channel-based charge injection in SOI MOSFET's under hot carrier stress

By operating one channel of a typical SOI MOSFET in avalanche while keeping the opposite channel accumulated, charge injection into the opposite gate takes place. Three independent experiments are described that demonstrate the occurrence of this opposite-channel based charge injection. The experimental results are in agreement with PISCES numerical simulations. >

Hot hole induced interface state generation and annihilation in SOI MOSFETs

The effects of pure hot hole injection in SOI MOSFETs are investigated. Pure hot hole injection is achieved by exploiting the opposite channel based carrier injection phenomenon. It is found that significant amounts of interface states are generated, some of which are annihilated by a subsequent hot electron injection pulse. A power law of the form D/sub it/(t)=Kt/sup n/ with n close to 0.25 was obtained, indicating a more complex, diffusion limited, electrochemical reaction at the interface than previously reported.

Generation and annihilation of interface states under alternate hot electron/hole injection in SOI MOSFET's

The sequential front/back stressing technique was recently shown to be a powerful tool for studying hot-carrier degradation mechanisms in SOI MOSFETs. In this paper we use this technique, coupled with charge pumping, to analyze the effect of alternate electron/hole injection on interface states in SOI MOSFETs. Since this technique employs pure hot majority carrier injection from the opposite channel, the effect of electron and hole injections can be studied independent of each other. We observe that interface state creation takes place at the front interface following both electron injection and hole injection.

Mechanisms of Hot-Carrier induced degradation of SOI (SIMOX) MOSFET's

Abstract An experimental study of the degradation mechanisms of hot-carrier stressed SOI (SIMOX) MOSFETs is carried out. Depending on the applied stress conditions, it is found that device degradation is mainly caused by electron and hole trapping by intrinsic and generated oxide traps and/or by generation of interfaces states. Sequential hot-electron stressing of the front/back channels results in successive electron/hole injection in the gate oxides, leading to important insights on the nature of the degradation mechanisms.

Common origin of hot carrier charging of gate and buried oxide in SOI (SIMOX) MOSFETs

Hot electron/hole trapping in the gate and buried oxides of SOI (SIMOX) MOSFETs is investigated by combining the sequential front/back channel hot-electron stressing technique and measurements of static transistor characteristics. In this technique pure hot-hole injection is achieved by keeping the channel accumulated while stressing the opposite channel under electron injection conditions. Three lots of PD devices (denoted 3A, 12A, and 15A) fabricated on SIMOX wafers with channel lengths down to 0.8 /spl mu/m were investigated. The main difference between these lots were in the drain design, in an effort to develop hot-electron resistant circuits for space/satellite applications.

Successive charging/discharging of gate oxides in SOI MOSFETs by sequential hot electron stressing of front/back channel

The purpose of this work is to demonstrate that hot electron stressing one channel in a SOI MOSFET can in fact inject charges into the other channel, and it discusses two important applications of this phenomenon: namely, that it can be used as a new tool for the study of the mechanisms of degradation, and for designing erasing schemes for SOI based flash memories. The measurements were performed on partially and fully depleted SIMOX MOSFETs with LDD and channel lengths down to 0.6 /spl mu/m.<<ETX>>

Generation lifetime measurements in fully depleted enhancement and accumulation mode SOI MOSFETs

In this work we present a unified analysis for both enhancement and accumulation mode devices, by considering the temporal variation of the quasi-Fermi levels. This leads to an accurate determination of the generation volume, and to Zerbst-type expressions for the drain current transients for enhancement equation and accumulation equation mode devices.<<ETX>>