S.P. Sinha

In depth analysis of opposite channel based charge injection in SOI MOSFETs and related defect creation and annihilation

Abstract Extensive PISCES simulations, incorporating non-local effects are carried out to obtain an in-depth understanding of the recently observed opposite channel based charge injection in SOI MOSFETs [1]. This charge injection is then combined with basic transistor characteristics and charge pumping current measurements to study the hot carrier degradation mechanisms in a variety of SOI MOSFETs, and clarify the separate roles played by hot electrons and holes in the degradation. It is also used as the basis for the design of a new, SOI based flash memory cell.

Opposite-channel-based injection of hot-carriers in SOI MOSFET's: physics and applications

An extensive study of the recently observed opposite-channel-based injection (OCBI) of hot-carriers in SOI MOSFETs is carried out by PISCES numerical calculations. The study reveals similar patterns of injection for partially-depleted (PD) and fully-depleted (FD) devices, although there are significant quantitative differences. Important differences also exist when stressing the device with the body floating versus body grounded. The results demonstrate that when stressing one channel, carriers can and are injected into the opposite gate. The results also demonstrate that under appropriate bias conditions pure electron/hole injection takes place, and establish these conditions. The practical significance of this ability to inject only electrons or only holes in any desired sequence is illustrated by exploiting it to investigate the time-power law of interface state generation and to design a SOI EEPROM cell with a back channel based erasing scheme.

Investigation of carrier generation in fully depleted enhancement and accumulation mode SOI MOSFET's

An unified dual gate Zerbst-like technique has been developed to extract the generation lifetime in enhancement and accumulation mode fully depleted SOI MOSFETs. The technique is based on the analysis of the temporal variation of the quasi Fermi levels in the devices, following the application of a suitable voltage step on one of the gates. The analysis resulted in simple Zerbst-like expressions for the drain current transients. Numerical simulations, using PISCES, have been performed to validate the technique and its underlying analysis. The technique has been applied to both kinds of typical fully depleted SIMOX SOI MOSFETs and the measured generation lifetimes were in the range of 0.1 /spl mu/s to 1.0 /spl mu/s. >

Time dependence power laws of hot carrier degradation in SOI MOSFETS

The opposite channel based charge injection phenomenon in SOI MOSFETs provides a powerful tool, as it makes it possible for the first time to inject only holes or only electrons in regular, working MOSFETs. In this paper opposite channel based hot carrier injection has been combined with charge pumping measurements and the effects of pure hot electron/hole injection were investigated. n channel devices were used for the pure hole injection experiments, and p channel ones for the electron injection. The results demonstrate that both pure hole and pure electron injection give rise to interface state generation obeying a time power law. Based on these and other results, a conclusion is drawn that the purity of the injection pulse is responsible for the time power law, regardless of whether holes or electrons are injected. In contrast, when bipolar injection (mixture of holes and electrons) was applied, our results showed a familiar pattern.

LDD design tradeoffs for single transistor latch-up and hot carrier degradation control in accumulation mode FD SOI MOSFET's

An experimental study has been conducted of the design tradeoffs of fully-depleted (FD) accumulation mode Silicon-on-Insulator (SOI) MOSFETs with regard to hot carrier reliability, single transistor latch-up and device performance. Three drain designs were considered, using Large-Tilt-Angle Implantation (LATID) for the LDD formation. Structures incorporating 0/spl deg/ angle LDD implant, large angle LDD implant, and no LDD were fabricated, and their hot carrier reliability, single transistor latch-up voltage, and device performance in terms of drive current and speed were determined. Correct interpretation of the experimental results was aided by performing PISCES numerical simulations. It was found that the structure with the best hot carrier reliability (large angle LDD implant) has the worst case latch-up voltage, and the one with the worst hot carrier reliability (no LDD implant) has the best latch-up voltage. Overall good device performance with acceptable hot carrier reliability and latch-up voltage is obtained with the 0/spl deg/ angle LDD implant.

Opposite-channel-based charge injection in SOI MOSFET's under hot carrier stress

By operating one channel of a typical SOI MOSFET in avalanche while keeping the opposite channel accumulated, charge injection into the opposite gate takes place. Three independent experiments are described that demonstrate the occurrence of this opposite-channel based charge injection. The experimental results are in agreement with PISCES numerical simulations. >

Hot hole induced interface state generation and annihilation in SOI MOSFETs

The effects of pure hot hole injection in SOI MOSFETs are investigated. Pure hot hole injection is achieved by exploiting the opposite channel based carrier injection phenomenon. It is found that significant amounts of interface states are generated, some of which are annihilated by a subsequent hot electron injection pulse. A power law of the form D/sub it/(t)=Kt/sup n/ with n close to 0.25 was obtained, indicating a more complex, diffusion limited, electrochemical reaction at the interface than previously reported.

Generation and annihilation of interface states under alternate hot electron/hole injection in SOI MOSFET's

The sequential front/back stressing technique was recently shown to be a powerful tool for studying hot-carrier degradation mechanisms in SOI MOSFETs. In this paper we use this technique, coupled with charge pumping, to analyze the effect of alternate electron/hole injection on interface states in SOI MOSFETs. Since this technique employs pure hot majority carrier injection from the opposite channel, the effect of electron and hole injections can be studied independent of each other. We observe that interface state creation takes place at the front interface following both electron injection and hole injection.

Common origin of hot carrier charging of gate and buried oxide in SOI (SIMOX) MOSFETs

Hot electron/hole trapping in the gate and buried oxides of SOI (SIMOX) MOSFETs is investigated by combining the sequential front/back channel hot-electron stressing technique and measurements of static transistor characteristics. In this technique pure hot-hole injection is achieved by keeping the channel accumulated while stressing the opposite channel under electron injection conditions. Three lots of PD devices (denoted 3A, 12A, and 15A) fabricated on SIMOX wafers with channel lengths down to 0.8 /spl mu/m were investigated. The main difference between these lots were in the drain design, in an effort to develop hot-electron resistant circuits for space/satellite applications.

SOI-specific hot-hole induced degradation in PD and FD transistors

Hot carrier related degradation and reliability of SOI devices has assumed recently increased importance. The purpose of this paper is to report two new effects in SOI MOSFETs, and the results of a detailed study of the substrate current. The first effect relates to recent reports claiming that during front gate electron injection stress, the degradation of the back channel is negligible. The second effect relates to the nature of the generation mechanisms of interface states during hot hole injection.