Aaron Yip
Micron Technology
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Publication
Featured researches published by Aaron Yip.
international solid-state circuits conference | 2016
Tomoharu Tanaka; Mark A. Helm; Tommaso Vali; Ramin Ghodsi; Koichi Kawai; Jae-Kwan Park; Shigekazu Yamada; Feng Pan; Yuichi Einaga; Ali Ghalam; Toru Tanzawa; Jason Guo; Takaaki Ichikawa; Erwin Yu; Satoru Tamada; Tetsuji Manabe; Jiro Kishimoto; Yoko Oikawa; Yasuhiro Takashima; Hidehiko Kuge; Midori Morooka; Ali Mohammadzadeh; Jong Kang; Jeff Tsai; Emanuele Sirizotti; Eric N. Lee; Luyen Vu; Yuxing Liu; Hoon Choi; Kwonsu Cheon
A planar floating-gate NAND technology has previously realized a 0.87Gb/mm2 memory density using 3b/cell [1] and achieved a minimum feature size for 16nm [2]. However, the development of planar NAND flash is expected to reach the scaling limit in a few technology generations. To break though this limit, a significant shift to 3D NAND flash has begun and several types of 3D memory cell structures have been proposed and discussed [3-5]. Recently a 3D V-NAND technology achieved 1.86Gb/mm2 using charge-trap cells and 3b/cell [6]. This paper presents a 3b/cell NAND flash memory utilizing a 3D floating gate (FG) technology that achieves 4.29Gb/mm2.
Archive | 2006
Dzung H. Nguyen; Benjamin Louie; Hagop A. Nazarian; Aaron Yip; Jin-Man Han
Archive | 2004
Benjamin Louie; Aaron Yip; Jin-Man Han
Archive | 2010
Xiaojun Yu; Jin-Man Han; Aaron Yip
Archive | 2013
Shigekazu Yamada; Aaron Yip
Archive | 2005
Benjamin Louie; Yunqiu Wan; Aaron Yip; Jin-Man Han
Archive | 2013
Aaron Yip
Archive | 2006
Hendrik Hartono; Benjamin Louie; Aaron Yip; Hagop A. Nazarian
Archive | 2008
Aaron Yip
Archive | 2009
Jin-Man Han; Aaron Yip