Abderazek Ben Abdallah

Graceful deadlock-free fault-tolerant routing algorithm for 3D Network-on-Chip architectures

Three-Dimensional Networks-on-Chip (3D-NoC) has been presented as an auspicious solution merging the high parallelism of Network-on-Chip (NoC) interconnect paradigm with the high-performance and lower interconnect-power of 3-dimensional integration circuits. However, 3D-NoC systems are exposed to a variety of manufacturing and design factors making them vulnerable to different faults that cause corrupted message transfer or even catastrophic system failures. Therefore, a 3D-NoC system should be fault-tolerant to transient malfunctions or permanent physical damages. In this paper, we present an efficient fault-tolerant routing algorithm, called Hybrid-Look-Ahead-Fault-Tolerant (HLAFT), which takes advantage of both local and look-ahead routing to boost the performance of 3D-NoC systems while ensuring fault-tolerance. A deadlock-recovery technique associated with HLAFT, named Random-Access-Buffer (RAB), is also presented. RAB takes advantage of look-ahead routing to detect and remove deadlock with no considerably additional hardware complexity. We implemented the proposed algorithm and deadlock-recovery technique on a real 3D-NoC architecture (3D-OASIS-NoC) and prototyped it on FPGA. Evaluation results show that the proposed algorithm performs better than XYZ, even when considering high fault-rates (i.e., >= 20%), and outperforms our previously designed Look-Ahead-Fault-Tolerant routing (LAFT) demonstrated in latency/flit reduction that can reach 12.5% and a throughput enhancement reaching 11.8% in addition to 7.2% dynamic-power saving thanks to the Power-management module integrated with HLAFT.

LA-XYZ: Low Latency, High Throughput Look-Ahead Routing Algorithm for 3D Network-on-Chip (3D-NoC) Architecture

Despite the higher scalability and parallelism integration offered by 2D-Network-on-Chip (NoC) over the traditional shared-bus based systems, it is still not an ideal solution for future large scale Systems-on-Chip (SoCs). Recently, merging NoC to the third dimension (3D-NoC) has been proposed as a promising solution offering lower power consumption and higher speed. One of the most important design choices for 3D-NoC implementation is the routing algorithm, as it controls the path decision that a flit has tofollow while traveling along the network. This has a direct impact on the overall system performance. In this paper, we present an efficient routing algorithm for 3D-NoC named Look-Ahead-XYZ (LA-XYZ). This algorithm aims to minimize the communication latency and power consumption while enhancing the system throughput. Comparison results with systems adopting two dimensional routing showed that, using JPEG encoder and Matrix applications, LA-XYZ reduces the communication latency with up to 44.9% and enhances the throughput that can reach the 45.3% while observing an average 15.9% reduction in terms of dynamic power.

Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoC

During this last decade, Network-on-Chips (NoC) have been proposed as a promising solution for future systems on chip design. It offers more scalability than the shared-bus based interconnection, allows more processors to operate concurrently. Because NoC has dedicated wires, performance can be predicted. In this context, we proposed a 2D-NoC named OASIS, which is a 4x4 mesh topology design using Wormhole switching and Stall-and-Go flow control scheme. Although OASIS-NoC has its advantages over the shared-bus based systems, it has also some limitations such as high power consumption, high cost communication, and low throughput. To overcome those limitations we propose a 3D-NoC (3D OASIS-NoC) which is an extension to our 2D OASIS-NoC. In this paper we describe the 3D OASIS-NoC architecture in a fair amount of detail and present preliminary evaluation results.

Advanced Design Issues for OASIS Network-on-Chip Architecture

Network-on-Chip (NoC) architectures provide a good way of realizing efficient interconnections and largely alleviate the limitations of bus-based solutions. NoC has emerged as a solution to problems exhibited by the shared bus communication approach in System-On-Chip (SoC) implementations including lack of scalability, clock skew, lack of support for concurrent communication and power consumption. The communication requirement of this paradigm is affected by architecture parameters such as topology, routing, buffer size etc. In this paper, we propose advanced optimization techniques for OASIS NoC, a NoC we previously designed. We describe the architecture and the novel optimization techniques in details. Hardware complexity and preliminary performance results are also given.

Hybrid Photonic NoC Based on Non-Blocking Photonic Switch and Light-Weight Electronic Router

In conventional hybrid PNoC systems, the end-to end optical data transfer is accompanied with electrical control functions including path-setup, acknowledgment, and tear-down. These functions directly a ect the performance and power characteristics of these circuit-switching based systems. In this paper, we propose a novel hybrid PNoC system, named PHENIC-II. 1 Thanks to the adopted non-blocking photonic switch and light-weight electronic router, PHENIC-II is capable of alleviating the congestion in the electronic control layer which is considered as the main source of latency and power overhead in hybrid PNoC systems. From the performance evaluation, we demonstrate that the proposed system has a better performance and low energy dissipation when compared to the previously proposed systems.

Efficient Router Architecture, Design and Performance Exploration for Many-Core Hybrid Photonic Network-on-Chip (2D-PHENIC)

Nowadays, increasing emerging application complexity and improvement in process technology have enabled the design of many-core processors with tens to hundreds of cores on a single chip. Photonic Network-on-Chips (PNoCs) have recently been proposed as an alternative approach with high performance-per-watt characteristics for intra-chip communication. While providing large bandwidth through WDM (Wavelength Division Multiplexing), the main design challenge of conventional hybrid PNoC lies in the control layer, which is generally used for path set-up and also for short message communication. In this paper, we propose architecture and design of an efficient router for control and communication in heterogeneous Many-core Hybrid Photonic Network-on-Chip (2D-PHENIC). In addition, we present detailed complexity and performance evaluation of the proposed architecture.

PHENIC: silicon photonic 3D-network-on-chip architecture for high-performance Heterogeneous many-core system-on-chip

Network-on-chip architectures can improve the scalability, performance, and power efficiency of general multiprocessor systems and application-specific heterogeneous multicore and many-core SoCs (MCSoCs). This interconnection paradigm when combined with 3D integration technology offers advantages over 2D NoC design, such as shorter wire length, higher packing density, and smaller footprint. However, since processor architects and semiconductor industries are heading towards complex and large system design consisting of hundreds of PEs, traditional fully 2D or 3D electronic NoC approaches are becoming not enough for providing significant large bandwidth with low-power consumption. Optical Network-on-Chip (ONoC) promises significant advantages over their electronic counterparts. In particular, they offer a potentially disruptive technology solution with fundamentally low power dissipation that remains independent of capacity while providing ultra-high throughput and minimal access latency. In this work, we propose a novel 3D hybrid architecture, named PHENIC 3D-ONoC, is based on our earlier proposed 3D OASIS-NoC1, which uses optical layer for high bandwidth transfer and an electric control layer for path control. We present architecture, design, and preliminary evaluation results in a fair amount of details.

Adaptive fault-tolerant architecture and routing algorithm for reliable many-core 3D-NoC systems

During the last few decades, Three-dimensional Network-on-Chips (3D-NoCs) have been showing their advantages against 2D-NoC architectures. This is thanks to the reduced average interconnect length and lower interconnect-power consumption inherited from Three-dimensional Integrated Circuits (3D-ICs). On the other hand, questions about their reliability is starting to arise. This issue is mainly caused by their complex nature where a single faulty transistor may cause intolerable performance degradation or even the entire system collapse. To ensure their correct functionality, 3D-NoC systems must be fault-tolerant to any short-term malfunction or permanent physical damage to ensure message delivery on time while minimizing the performance degradation as much as possible.In this paper, we present a fault-tolerant 3D-NoC architecture, called 3D-Fault-Tolerant-OASIS (3D-FTO).11This project is partially supported by Competitive research funding, Ref. P1-5, Fukushima, Japan. With the aid of a light-weight routing algorithm, 3D-FTO manages to avoid the system failure at the presence of a large number of transient, intermittent, and permanent faults. Moreover, the proposed architecture is leveraging on reconfigurable components to handle the fault occurrence in links, input-buffers, and crossbar, where the faults are more often to happen. The proposed 3D-FTO system is able to work around different kinds of faults ensuring graceful performance degradation while minimizing the additional hardware complexity and remaining power-efficient. Adaptive fault-tolerant 3D-Network-on-Chip system architecture.RAB mechanism for deadlock recovery and fault-tolerance in input-buffers.Traffic-Prediction-Unit technique for congestion relief.Bypass-Link-on-Demand to tackle fault-occurrence in the Crossbar.Fault-tolerance and graceful performance degradation obtained at high fault-rates.

Hybrid silicon-photonic network-on-chip for future generations of high-performance many-core systems

Photonic networks-on-chip (PNoCs) promise significant advantages over their electronic counterparts. In particular, they offer a potentially disruptive technology solution with fundamentally low power dissipation that remains independent of capacity while providing ultra-high throughput and minimal access latency. In conventional hybrid-PNoC systems, several electrical control functions, such as path setup, acknowledgment and Tear-down are necessary for the end-to-end optical transfer. However, the circuit-switched nature of photonic interconnect directly affects the performance and power characteristics of on-chip communication. In this paper, we propose an energy-efficient and high-throughput hybrid silicon-photonic network-on-chip, named PHENIC, targeted for future generations of high-performance many-core systems. PHENIC is based on a smart contention-aware path-configuration algorithm and an energy-efficient non-blocking optical switch to further exploit the low energy proprieties of the PNoC systems. Through detailed simulation, we demonstrate that the proposed system has a better performance and low energy dissipation compared to conventional hybrid-PNoCs.Photonic networks-on-chip (PNoCs) promise significant advantages over their electronic counterparts. In particular, they offer a potentially disruptive technology solution with fundamentally low power dissipation that remains independent of capacity while providing ultra-high throughput and minimal access latency. In conventional hybrid-PNoC systems, several electrical control functions, such as path setup, acknowledgment and Tear-down are necessary for the end-to-end optical transfer. However, the circuit-switched nature of photonic interconnect directly affects the performance and power characteristics of on-chip communication. In this paper, we propose an energy-efficient and high-throughput hybrid silicon-photonic network-on-chip, named PHENIC, targeted for future generations of high-performance many-core systems. PHENIC is based on a smart contention-aware path-configuration algorithm and an energy-efficient non-blocking optical switch to further exploit the low energy proprieties of the PNoC systems. Through detailed simulation, we demonstrate that the proposed system has a better performance and low energy dissipation compared to conventional hybrid-PNoCs.

Contention-Free Routing for Hybrid Photonic Mesh-Based Network-on-Chip Systems

Photonic Networks-on-Chip (PNoCs) have emerged as an auspicious solution to solve the interconnect bottleneck found in their electronic counterparts. Thanks to their low-power properties and the tremendous achieved throughput, PNoCs are presented as highly scalable architectures that can satisfy the requirements of future generation many-core systems. In conventional hybrid PNoC systems, the path-setup algorithm determines the route and the required resources necessary for the end-to-end optical data transfer. Thus, this algorithm should be carefully designed as it plays a crucial role in determining the performance and power efficiency of such systems. In this paper, we present a contention-free routing for photonic mesh-based network-on-chip systems. The algorithm allows data and control/configuration signals to be transferred in the optical network. When implemented on our PHENIC-II system, evaluation results show that the End-to-End (ETE) latency is reduced by 40% and the overall energy of the electronic control module is reduced by 23% when compared to conventional hybrid PNoC systems.