Yuichi Okuyama

Hybrid Photonic NoC Based on Non-Blocking Photonic Switch and Light-Weight Electronic Router

In conventional hybrid PNoC systems, the end-to end optical data transfer is accompanied with electrical control functions including path-setup, acknowledgment, and tear-down. These functions directly a ect the performance and power characteristics of these circuit-switching based systems. In this paper, we propose a novel hybrid PNoC system, named PHENIC-II. 1 Thanks to the adopted non-blocking photonic switch and light-weight electronic router, PHENIC-II is capable of alleviating the congestion in the electronic control layer which is considered as the main source of latency and power overhead in hybrid PNoC systems. From the performance evaluation, we demonstrate that the proposed system has a better performance and low energy dissipation when compared to the previously proposed systems.

Efficient Router Architecture, Design and Performance Exploration for Many-Core Hybrid Photonic Network-on-Chip (2D-PHENIC)

Nowadays, increasing emerging application complexity and improvement in process technology have enabled the design of many-core processors with tens to hundreds of cores on a single chip. Photonic Network-on-Chips (PNoCs) have recently been proposed as an alternative approach with high performance-per-watt characteristics for intra-chip communication. While providing large bandwidth through WDM (Wavelength Division Multiplexing), the main design challenge of conventional hybrid PNoC lies in the control layer, which is generally used for path set-up and also for short message communication. In this paper, we propose architecture and design of an efficient router for control and communication in heterogeneous Many-core Hybrid Photonic Network-on-Chip (2D-PHENIC). In addition, we present detailed complexity and performance evaluation of the proposed architecture.

Contention-Free Routing for Hybrid Photonic Mesh-Based Network-on-Chip Systems

Photonic Networks-on-Chip (PNoCs) have emerged as an auspicious solution to solve the interconnect bottleneck found in their electronic counterparts. Thanks to their low-power properties and the tremendous achieved throughput, PNoCs are presented as highly scalable architectures that can satisfy the requirements of future generation many-core systems. In conventional hybrid PNoC systems, the path-setup algorithm determines the route and the required resources necessary for the end-to-end optical data transfer. Thus, this algorithm should be carefully designed as it plays a crucial role in determining the performance and power efficiency of such systems. In this paper, we present a contention-free routing for photonic mesh-based network-on-chip systems. The algorithm allows data and control/configuration signals to be transferred in the optical network. When implemented on our PHENIC-II system, evaluation results show that the End-to-End (ETE) latency is reduced by 40% and the overall energy of the electronic control module is reduced by 23% when compared to conventional hybrid PNoC systems.

Non-blocking electro-optic network-on-chip router for high-throughput and low-power many-core systems

Photonic Networks-on-Chip (PNoCs) have been proposed as a promising solution to solve the problems of their electronic counterparts. By offering low latency, ultra-high throughput and low power dissipation, PNoCs have opened a new horizon for future generation of many-core systems. An optical router for routing and flow control functions is the backbone component for these networks. In this paper, we propose a new non-blocking electro-optic router integrated in a mesh-based NoC system (PHENIC)1. When compared to similar non-blocking based architecture, the evaluation results show that the proposed router reduces the End-To-End latency by 40%. In addition, evaluation results show a considerable improvement in terms of energy consumption by up to 44%.

FTTDOR: Microring Fault-resilient Optical Router for Reliable Optical Network-on-Chip Systems

Photonic Networks-on-Chip (PNoCs) have been proposed as a disruptive technology solution to the silicon problem showing their great superiority over their electronic counterparts. In these architectures, higher bandwidth can be achieved thanks to the light speed transmissions, and the power required to transmit over a distance is much lower. Despite these advantages, PNoC designs are very complex, and thus are more susceptible to physical defects and short-term malfunctions. Therefore, fault-tolerance has become a primordial requirement for these future generation high-performance systems. In this paper, we present a fault-tolerant optical router, named FTTDOR, with its electrical control module for highly reliable low-power 3D-Networks-on-Chip (PHENIC). It uses minimal redundancy to assure accuracy of the packet transmission even after faulty Microring Resonators (MRs) are detected. The fault-tolerant optical switch is decomposed nonblocking, with minimal MRs, and requires no MRs for straight transmission (East to West, North to South, and Up to Down, as well as their inverses). Simulation results show that the network can maintain 98% and 94% throughput when considering 3% and 20% fault-rates, respectively. These results come with 35% decrease in the number of MRs when compared to the conventional crossbar switch resulting in 32% power reduction.

Adaptive Error- and Traffic-Aware Router Architecture for 3D Network-on-Chip Systems

The advent of deep sub-micron and 3D integration technologies has exacerbated reliability issues in packet-switched on-chip interconnection networks. A lot of researches have been conducted in order to make these systems immune to any short-term malfunction or permanent physical damage while minimizing the performance degradation as much as possible. In this paper, we present an adaptive Error-, and Traffic-aware 3D-NoC router architecture, called 3D-Fault-Tolerant-OASIS (3D-FTO). 3D-FTO manages to avoid the system failure at the presence of a large number of faults and addresses the fault occurrence in links, input-buffers, and the crossbar, where the faults are more often to happen. The proposed 3D-FTO system was synthesized using Synopsis Design Compiler at 45nm CMOS process technology. Evaluation results show that our 3D-FTO is able to work around different kinds of faults ensuring graceful performance degradation while minimizing the additional hardware complexity and remaining power-efficient.

A Hardware Resource Management System for Adaptive Computing on Dynamically Reconfigurable Devices

This paper proposes a realization method of the computer system with dynamical hardware-resource allocation on dynamically reconfigurable devices. The system consists of two or more parts and they can change the number of processing units according to each processing load. In the system, there is a competition problem between these parts. In order to solve this problem, we investigate required functions of resource management units on a simple processing model. This model is an adapted load balancing model consisting of an upper management unit, two management units and processing units shared by them

A low-overhead soft---hard fault-tolerant architecture, design and management scheme for reliable high-performance many-core 3D-NoC systems

The Network-on-Chip (NoC) paradigm has been proposed as a favorable solution to handle the strict communication requirements between the increasingly large number of cores on a single chip. However, NoC systems are exposed to the aggressive scaling down of transistors, low operating voltages, and high integration and power densities, making them vulnerable to permanent (hard) faults and transient (soft) errors. A hard fault in a NoC can lead to external blocking, causing congestion across the whole network. A soft error is more challenging because of its silent data corruption, which leads to a large area of erroneous data due to error propagation, packet re-transmission, and deadlock. In this paper, we present the architecture and design of a comprehensive soft error and hard fault-tolerant 3D-NoC system, named 3D-Hard-Fault-Soft-Error-Tolerant-OASIS-NoC (3D-FETO). With the aid of efficient mechanisms and algorithms, 3D-FETO is capable of detecting and recovering from soft errors which occur in the routing pipeline stages and leverages reconfigurable components to handle permanent faults in links, input buffers, and crossbars. In-depth evaluation results show that the 3D-FETO system is able to work around different kinds of hard faults and soft errors, ensuring graceful performance degradation, while minimizing additional hardware complexity and remaining power efficient.

A master-slave adaptive load-distribution processor model on PCA

In this paper, we propose a new load-distribution processor model that adapts hardware resources optimally and autonomously to target applications on dynamical reconfiguration devices. In the procedure of load-distribution, the processor detects the load of task-processing by itself and changes the kinds and number of resources optimally. We adopt the master-slave model, which consists of a management unit (master) and two or more processing units (slaves). The former detects overload and distributes tasks and the latter execute task-processing. One of the features of this model is that it is possible to change the number of processing units without reconfiguring the management units structure. Moreover, in order to use this load-distribution system efficiently, we propose a reordering unit that buffers data from processing units and outputs rearranged data. In this paper, we describe the requirements and organization of a management unit and processing units. Next, we implement the proposed model on real chips of PCA, a dynamical reconfiguration device, and measure the overheads of processing and reconfiguration. Finally, we evaluate the proposed model based on the experimental results. From the experiments, we show that our proposed model can reduce a designers efforts to estimate the amount of hardware resources according to applications in advance.

Hardware implementation of shading models in an application specific integrated circuit

The Truga001 is a single chip rendering processor with 12 embedded graphics functions. Phong and bump mapped shading, reflection and reflection mapping, gaseous object rendering and video mapping are incorporated fully in hardware with a MIMD structure. Shaded and texture mapped pixels are rendered at 3.8 ns/pixel which is equivalent to 1.2 million triangle polygons (100 pixels/s) with hidden surface removal. In the design of the Phong and bump mapped shading circuit, we used angular parameters for defining surface and light source normals instead of vector. This enables the circuit-scale less than 10000 gates/circuit. The chip is fabricated with a 940000 gate standard cell, 0.3 /spl mu/m CMOS in a TCP/BGA package. The paper describes the hardware architecture and its implementation technologies of the Phong and bump mapped shading in an ASIC.