Achraf Ben Ahmed

Hybrid Photonic NoC Based on Non-Blocking Photonic Switch and Light-Weight Electronic Router

In conventional hybrid PNoC systems, the end-to end optical data transfer is accompanied with electrical control functions including path-setup, acknowledgment, and tear-down. These functions directly a ect the performance and power characteristics of these circuit-switching based systems. In this paper, we propose a novel hybrid PNoC system, named PHENIC-II. 1 Thanks to the adopted non-blocking photonic switch and light-weight electronic router, PHENIC-II is capable of alleviating the congestion in the electronic control layer which is considered as the main source of latency and power overhead in hybrid PNoC systems. From the performance evaluation, we demonstrate that the proposed system has a better performance and low energy dissipation when compared to the previously proposed systems.

Efficient Router Architecture, Design and Performance Exploration for Many-Core Hybrid Photonic Network-on-Chip (2D-PHENIC)

Nowadays, increasing emerging application complexity and improvement in process technology have enabled the design of many-core processors with tens to hundreds of cores on a single chip. Photonic Network-on-Chips (PNoCs) have recently been proposed as an alternative approach with high performance-per-watt characteristics for intra-chip communication. While providing large bandwidth through WDM (Wavelength Division Multiplexing), the main design challenge of conventional hybrid PNoC lies in the control layer, which is generally used for path set-up and also for short message communication. In this paper, we propose architecture and design of an efficient router for control and communication in heterogeneous Many-core Hybrid Photonic Network-on-Chip (2D-PHENIC). In addition, we present detailed complexity and performance evaluation of the proposed architecture.

PHENIC: silicon photonic 3D-network-on-chip architecture for high-performance Heterogeneous many-core system-on-chip

Network-on-chip architectures can improve the scalability, performance, and power efficiency of general multiprocessor systems and application-specific heterogeneous multicore and many-core SoCs (MCSoCs). This interconnection paradigm when combined with 3D integration technology offers advantages over 2D NoC design, such as shorter wire length, higher packing density, and smaller footprint. However, since processor architects and semiconductor industries are heading towards complex and large system design consisting of hundreds of PEs, traditional fully 2D or 3D electronic NoC approaches are becoming not enough for providing significant large bandwidth with low-power consumption. Optical Network-on-Chip (ONoC) promises significant advantages over their electronic counterparts. In particular, they offer a potentially disruptive technology solution with fundamentally low power dissipation that remains independent of capacity while providing ultra-high throughput and minimal access latency. In this work, we propose a novel 3D hybrid architecture, named PHENIC 3D-ONoC, is based on our earlier proposed 3D OASIS-NoC1, which uses optical layer for high bandwidth transfer and an electric control layer for path control. We present architecture, design, and preliminary evaluation results in a fair amount of details.

Hybrid silicon-photonic network-on-chip for future generations of high-performance many-core systems

Photonic networks-on-chip (PNoCs) promise significant advantages over their electronic counterparts. In particular, they offer a potentially disruptive technology solution with fundamentally low power dissipation that remains independent of capacity while providing ultra-high throughput and minimal access latency. In conventional hybrid-PNoC systems, several electrical control functions, such as path setup, acknowledgment and Tear-down are necessary for the end-to-end optical transfer. However, the circuit-switched nature of photonic interconnect directly affects the performance and power characteristics of on-chip communication. In this paper, we propose an energy-efficient and high-throughput hybrid silicon-photonic network-on-chip, named PHENIC, targeted for future generations of high-performance many-core systems. PHENIC is based on a smart contention-aware path-configuration algorithm and an energy-efficient non-blocking optical switch to further exploit the low energy proprieties of the PNoC systems. Through detailed simulation, we demonstrate that the proposed system has a better performance and low energy dissipation compared to conventional hybrid-PNoCs.Photonic networks-on-chip (PNoCs) promise significant advantages over their electronic counterparts. In particular, they offer a potentially disruptive technology solution with fundamentally low power dissipation that remains independent of capacity while providing ultra-high throughput and minimal access latency. In conventional hybrid-PNoC systems, several electrical control functions, such as path setup, acknowledgment and Tear-down are necessary for the end-to-end optical transfer. However, the circuit-switched nature of photonic interconnect directly affects the performance and power characteristics of on-chip communication. In this paper, we propose an energy-efficient and high-throughput hybrid silicon-photonic network-on-chip, named PHENIC, targeted for future generations of high-performance many-core systems. PHENIC is based on a smart contention-aware path-configuration algorithm and an energy-efficient non-blocking optical switch to further exploit the low energy proprieties of the PNoC systems. Through detailed simulation, we demonstrate that the proposed system has a better performance and low energy dissipation compared to conventional hybrid-PNoCs.

Contention-Free Routing for Hybrid Photonic Mesh-Based Network-on-Chip Systems

Photonic Networks-on-Chip (PNoCs) have emerged as an auspicious solution to solve the interconnect bottleneck found in their electronic counterparts. Thanks to their low-power properties and the tremendous achieved throughput, PNoCs are presented as highly scalable architectures that can satisfy the requirements of future generation many-core systems. In conventional hybrid PNoC systems, the path-setup algorithm determines the route and the required resources necessary for the end-to-end optical data transfer. Thus, this algorithm should be carefully designed as it plays a crucial role in determining the performance and power efficiency of such systems. In this paper, we present a contention-free routing for photonic mesh-based network-on-chip systems. The algorithm allows data and control/configuration signals to be transferred in the optical network. When implemented on our PHENIC-II system, evaluation results show that the End-to-End (ETE) latency is reduced by 40% and the overall energy of the electronic control module is reduced by 23% when compared to conventional hybrid PNoC systems.

Non-blocking electro-optic network-on-chip router for high-throughput and low-power many-core systems

Photonic Networks-on-Chip (PNoCs) have been proposed as a promising solution to solve the problems of their electronic counterparts. By offering low latency, ultra-high throughput and low power dissipation, PNoCs have opened a new horizon for future generation of many-core systems. An optical router for routing and flow control functions is the backbone component for these networks. In this paper, we propose a new non-blocking electro-optic router integrated in a mesh-based NoC system (PHENIC)1. When compared to similar non-blocking based architecture, the evaluation results show that the proposed router reduces the End-To-End latency by 40%. In addition, evaluation results show a considerable improvement in terms of energy consumption by up to 44%.

Hardware/software prototyping of dependable real-time system for elderly health monitoring

Recent technological advances in sensors, low-power microelectronics, and wireless networking enabled the proliferation of wireless sensor networks for wide applications. One of the promising applications of this domain is the distributed remote health monitoring of elderly people. An effective approach to speed up this and other bio-medical applications is to integrate a very high number of processing elements in a single chip so that the massive scale of fine-grain parallelism inherent in several bio-medical applications can be exploited efficiently. In this work, we present architecture and preliminary prototyping results of a novel dependable real-time system (BANSMOM1) targeted for elderly health monitoring. The proposed system achieves its real-time performance via parallel processing technique and a so called period-peak detection algorithm (PPD) for processing multi-lead Electrocardiography records.

Architecture and design of real-time system for elderly health monitoring

Despite the decreased human mortality rate, heart disorders are one of the main causes of death around the world. As a result, detection of irregularities in the rhythms of the heart is a growing concern in medical researches. The collection, processing, and visualisation of such biomedical data in real-time is a challenging task due to the large amounts of data that need to be processed, especially when the records are made for a long time. Recent technological advances in sensors and low-power microelectronics enabled the development of a single embedded biomedical chip capable of running computationally intensive biomedical applications, such as remote analysis and monitoring of human heart activity, which is still a challenging problem for biomedical engineers. In this work, we present a novel architecture and hardware/software prototyping of a real-time system, targeted for elderly health monitoring, named BANSMOM. The proposed system achieves its real-time performance via parallel processing techniques and a period-peak-detection algorithm (PPD) for processing multi-lead electrocardiography records in parallel. We tested the proposed system with real ECG fixed length records (10 s/sample) from the MIT database. From the evaluation results, we found that the system meets its real-time requirements and achieves about 69% accuracy.

Scalable Photonic Networks-on-Chip Architecture Based on a Novel Wavelength-Shifting Mechanism

Since Photonic Networks-on-Chip (PNoCs) were proposed, there was an unanimity about the benefits that photonic links could bring to the on-chip interconnection. However, a debate always takes place regarding the suitable architecture and routing scheme to be used. This debate concerns the use of fully photonic PNoC or an Electro-assisted one. Both schemes have their pros and cons, but the main drawback in both architectures is their scalability. We propose in this paper an alternative to these two conventional PNoC architectures. Our proposed system is based on a novel Wavelength-Shifting mechanism, which combines the benefits of the previously mentioned schemes while limiting their drawbacks. The proposed system was validated by an analytical model, in addition to a set of simulations using synthetic and realistic traffic patterns. Evaluation results show that compared to the electro-assisted architectures, we could enhance the latency, power, and bandwidth by an order of magnitude, reaching a performance similar to the fully photonic architecture. In addition, the number of used photonic devices still much lower than the one used in conventional fully photonic architectures by an average of 60 percent. Furthermore, the new wavelength-shifting mechanism is highly scalable, and it is not affected anymore by the communications distance, nor the traffic pattern, which make it a promising solution to replace existing conventional architectures.