Akram Ben Ahmed

Graceful deadlock-free fault-tolerant routing algorithm for 3D Network-on-Chip architectures

Three-Dimensional Networks-on-Chip (3D-NoC) has been presented as an auspicious solution merging the high parallelism of Network-on-Chip (NoC) interconnect paradigm with the high-performance and lower interconnect-power of 3-dimensional integration circuits. However, 3D-NoC systems are exposed to a variety of manufacturing and design factors making them vulnerable to different faults that cause corrupted message transfer or even catastrophic system failures. Therefore, a 3D-NoC system should be fault-tolerant to transient malfunctions or permanent physical damages. In this paper, we present an efficient fault-tolerant routing algorithm, called Hybrid-Look-Ahead-Fault-Tolerant (HLAFT), which takes advantage of both local and look-ahead routing to boost the performance of 3D-NoC systems while ensuring fault-tolerance. A deadlock-recovery technique associated with HLAFT, named Random-Access-Buffer (RAB), is also presented. RAB takes advantage of look-ahead routing to detect and remove deadlock with no considerably additional hardware complexity. We implemented the proposed algorithm and deadlock-recovery technique on a real 3D-NoC architecture (3D-OASIS-NoC) and prototyped it on FPGA. Evaluation results show that the proposed algorithm performs better than XYZ, even when considering high fault-rates (i.e., >= 20%), and outperforms our previously designed Look-Ahead-Fault-Tolerant routing (LAFT) demonstrated in latency/flit reduction that can reach 12.5% and a throughput enhancement reaching 11.8% in addition to 7.2% dynamic-power saving thanks to the Power-management module integrated with HLAFT.

LA-XYZ: Low Latency, High Throughput Look-Ahead Routing Algorithm for 3D Network-on-Chip (3D-NoC) Architecture

Despite the higher scalability and parallelism integration offered by 2D-Network-on-Chip (NoC) over the traditional shared-bus based systems, it is still not an ideal solution for future large scale Systems-on-Chip (SoCs). Recently, merging NoC to the third dimension (3D-NoC) has been proposed as a promising solution offering lower power consumption and higher speed. One of the most important design choices for 3D-NoC implementation is the routing algorithm, as it controls the path decision that a flit has tofollow while traveling along the network. This has a direct impact on the overall system performance. In this paper, we present an efficient routing algorithm for 3D-NoC named Look-Ahead-XYZ (LA-XYZ). This algorithm aims to minimize the communication latency and power consumption while enhancing the system throughput. Comparison results with systems adopting two dimensional routing showed that, using JPEG encoder and Matrix applications, LA-XYZ reduces the communication latency with up to 44.9% and enhances the throughput that can reach the 45.3% while observing an average 15.9% reduction in terms of dynamic power.

Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoC

During this last decade, Network-on-Chips (NoC) have been proposed as a promising solution for future systems on chip design. It offers more scalability than the shared-bus based interconnection, allows more processors to operate concurrently. Because NoC has dedicated wires, performance can be predicted. In this context, we proposed a 2D-NoC named OASIS, which is a 4x4 mesh topology design using Wormhole switching and Stall-and-Go flow control scheme. Although OASIS-NoC has its advantages over the shared-bus based systems, it has also some limitations such as high power consumption, high cost communication, and low throughput. To overcome those limitations we propose a 3D-NoC (3D OASIS-NoC) which is an extension to our 2D OASIS-NoC. In this paper we describe the 3D OASIS-NoC architecture in a fair amount of detail and present preliminary evaluation results.

Adaptive fault-tolerant architecture and routing algorithm for reliable many-core 3D-NoC systems

During the last few decades, Three-dimensional Network-on-Chips (3D-NoCs) have been showing their advantages against 2D-NoC architectures. This is thanks to the reduced average interconnect length and lower interconnect-power consumption inherited from Three-dimensional Integrated Circuits (3D-ICs). On the other hand, questions about their reliability is starting to arise. This issue is mainly caused by their complex nature where a single faulty transistor may cause intolerable performance degradation or even the entire system collapse. To ensure their correct functionality, 3D-NoC systems must be fault-tolerant to any short-term malfunction or permanent physical damage to ensure message delivery on time while minimizing the performance degradation as much as possible.In this paper, we present a fault-tolerant 3D-NoC architecture, called 3D-Fault-Tolerant-OASIS (3D-FTO).11This project is partially supported by Competitive research funding, Ref. P1-5, Fukushima, Japan. With the aid of a light-weight routing algorithm, 3D-FTO manages to avoid the system failure at the presence of a large number of transient, intermittent, and permanent faults. Moreover, the proposed architecture is leveraging on reconfigurable components to handle the fault occurrence in links, input-buffers, and crossbar, where the faults are more often to happen. The proposed 3D-FTO system is able to work around different kinds of faults ensuring graceful performance degradation while minimizing the additional hardware complexity and remaining power-efficient. Adaptive fault-tolerant 3D-Network-on-Chip system architecture.RAB mechanism for deadlock recovery and fault-tolerance in input-buffers.Traffic-Prediction-Unit technique for congestion relief.Bypass-Link-on-Demand to tackle fault-occurrence in the Crossbar.Fault-tolerance and graceful performance degradation obtained at high fault-rates.

FTTDOR: Microring Fault-resilient Optical Router for Reliable Optical Network-on-Chip Systems

Photonic Networks-on-Chip (PNoCs) have been proposed as a disruptive technology solution to the silicon problem showing their great superiority over their electronic counterparts. In these architectures, higher bandwidth can be achieved thanks to the light speed transmissions, and the power required to transmit over a distance is much lower. Despite these advantages, PNoC designs are very complex, and thus are more susceptible to physical defects and short-term malfunctions. Therefore, fault-tolerance has become a primordial requirement for these future generation high-performance systems. In this paper, we present a fault-tolerant optical router, named FTTDOR, with its electrical control module for highly reliable low-power 3D-Networks-on-Chip (PHENIC). It uses minimal redundancy to assure accuracy of the packet transmission even after faulty Microring Resonators (MRs) are detected. The fault-tolerant optical switch is decomposed nonblocking, with minimal MRs, and requires no MRs for straight transmission (East to West, North to South, and Up to Down, as well as their inverses). Simulation results show that the network can maintain 98% and 94% throughput when considering 3% and 20% fault-rates, respectively. These results come with 35% decrease in the number of MRs when compared to the conventional crossbar switch resulting in 32% power reduction.

Adaptive Error- and Traffic-Aware Router Architecture for 3D Network-on-Chip Systems

The advent of deep sub-micron and 3D integration technologies has exacerbated reliability issues in packet-switched on-chip interconnection networks. A lot of researches have been conducted in order to make these systems immune to any short-term malfunction or permanent physical damage while minimizing the performance degradation as much as possible. In this paper, we present an adaptive Error-, and Traffic-aware 3D-NoC router architecture, called 3D-Fault-Tolerant-OASIS (3D-FTO). 3D-FTO manages to avoid the system failure at the presence of a large number of faults and addresses the fault occurrence in links, input-buffers, and the crossbar, where the faults are more often to happen. The proposed 3D-FTO system was synthesized using Synopsis Design Compiler at 45nm CMOS process technology. Evaluation results show that our 3D-FTO is able to work around different kinds of faults ensuring graceful performance degradation while minimizing the additional hardware complexity and remaining power-efficient.

On the Design of a Fault-Tolerant Photonic Network-on-Chip

Optical Network-on-Chip is a solution to for power and throughput bottlenecks of current technology. The higher bandwidth is achieved by the light speed transmissions, and the power required to transmit data in the optical domain is much lower. This is a disruptive technology solution to problems arising from silicon-based computing. In this paper, we present a fault-tolerant optical router (FTTDOR) with its electrical control module towards the design of a highly-reliable low-power three dimensional Networks-on-Chip (PHENIC). FTTDOR uses redundancy only in critical locations, to assure accuracy of the packet transmission even after a faulty ring resonator appears. The proposed optical router is decomposed non-blocking, with minimal ring resonators, and requires no resonators for straight travel (East to West, North to South, and Up to Down, as well as their inverses). Simulation results show that the network can maintain a 98% throughput after 3% faults, and 89% after 20% faults. These results come with a reduction of micro-ring resonators to 65% of the amount present in a conventional crossbar router. Simulation of the electrical control module and router show that it has a total area of around 20,000 μm2 and consumes 3.8mW at 600MHz.

MuCCRA4-BB: A fine-grained body biasing capable DRP

The partitioning, implementation and in-silicon leakage evaluation of MuCCRA4-BB proved the feasibility and validity of fine-grained BB. Furthermore, it demonstrated the superiority over coarse- and chip-grained BB, minimizing FBB leakage penalty and allowing far more RBB usage in all applications and scenarios. As leakage exacerbates in smaller geometries, fine-grained BB might be an answer with sensible overhead.

Asymmetric Body Bias Control With Low-Power FD-SOI Technologies: Modeling and Power Optimization

Body bias control is a fundamental technique widely used to provide an efficient tradeoff between leakage power and performance in ultralow-power systems. Therefore, a lot of research about power optimization which provides optimal power supply and body bias voltages has been carried out. However, considering the actual voltage sources, the conventional approaches suffer from limited performance/power control granularity and may lead to degradation in terms of the energy efficiency. Therefore, in this paper, a power optimization method that improves the performance/power control granularity is proposed and evaluated with real processor chips. In the proposed optimization, the body biases for nMOSFET and pMOSFET are controlled independently, while the conventional methods control them uniformly. This increases the number of possible voltage combinations and allows finer target frequency selection leading to lower power consumption than the conventional methods at the cost of the optimization complexity. In order to ease this complexity, the proposed optimization is based on simple power and delay models. The model-based optimization does not require brute force search in the phase of real chip testing; thus, the testing time and cost can be significantly reduced. Since the coefficients of the models are extracted with real chip measurements, the error of the model can be suppressed to a few percent in average. The proposed approach is validated by real chips implemented with a 65-nm fully depleted silicon on insulator technology. The evaluation results show that the proposed optimization is an efficient mean of power reduction for a leakage current dominant chip. In fact, when compared with the conventional method, the proposed approach achieves 9.617% of average power reduction reaching up to 22.77% in the case of the V850 microcontroller.

Digitally Assisted On-Chip Body Bias Tuning Scheme for Ultra Low-Power VLSI Systems

Body bias control is one of the most efficient means to reduce leakage power, adjust process variation, and apply performance boost. However, such control incurs a certain power overhead that has to be reduced, especially in ultra low-power systems. In order to exploit the advantages of body bias control while guaranteeing power efficiency, an on-chip control scheme is required. Conventionally, on-chip body bias control relies on the use of digital–analog converters. However, such analog circuits require a high power supply voltage and an additional power source, resulting in a considerable power overhead and an increased system cost. In this paper, an on-chip “Digitally assisted Automatic Body-bias Tuning” (DABT) scheme for ultra low-power systems is proposed and evaluated. The proposed scheme controls the body bias voltage so as to meet the timing constraints of a given target system. Since DABT is based on “Digitally assisted” circuitries, it can decrease the power supply voltage to near-threshold region and, therefore, a significant amount of power overhead can be reduced. The proposed system is fabricated with the 65-nm silicon on thin box (SOTB) process, a fully depleted silicon on insulator technology. We demonstrate that the chip can achieve the expected functionality, even with 0.35 V of power supply voltage, and with only a few micro watts of power overhead. Moreover, the efficiency of the proposed system is evaluated with a MIPS processor, adopted as a case study. According to the obtained evaluation results, the proposed system can enable 80% of leakage reduction while maintaining the frequency required to meet the timing constraints of the adopted target MIPS processor.