Abhay Saxena

Designing Power Efficient Fibonacci Generator Using Different FPGA Families

In consideration to wireless communication Fibonacci number is used to generate WPA and WPA2 (Wi-Fi Protected Access) key. Here, in our work we have designed green Fibonacci Generator under different FPGA families. Families we taken into consideration is Automotive Artix7, Artix7 and Kintex7. First we have calculated power consumption of our designed at 2Volt & 1GHz frequency and change the capacitance from 5 to 30pf and found there is tiny changes in Artix7and kintex7 Family but got significant changes in Automotive Artix7 around 16.79%. Secondly we have calculated power consumption of our designed at 2Volt & 10 GHz frequency and change the capacitance from 5 to 30pf, and found 41.09%, 13.95% and 38.06% change respectively for Automotive Artix7, Artix7 and Kintex7 FPGA families. Third we have worked with 3V and 1 GHz and got tiny changes with Artix7 and Kintex7 and found error value with Automotive Artix7. Lastly we have worked with 3V and 10 GHz and changed the capacitance from 5 to 30pf, we got 4.7% and 30.10% significant reduction in power consumption for Artix7 and Kintex7 FPGA families but for Automotive Artix7 we again got error value. Keyword Artix7, kentix7, FPGA, Energy Efficient Design

Cloud forecaster: Gizmo for Evaluation of Bulky Cloud Computing Surroundings to Propagate ICT based Education

Abstract-In recent year cloud computing become one of the rapid advancement field in computer science, which offers to access remote server for storing and retrieving our data. In this paper, we have used Cloudanalyst tool to determine load balancing factor, response time and cost of our data center for developing ICT based Education through Mobile Application. For analyzing our result, we have used 3 and 7 Data Centers and used Round Robin algorithm. For algorithm simulation, we have used five user bases named as UB1, UB2, UB3, UB4, UB5 and region R2. In our work, we basically concentrated on calculated Response Time and Data Center processing time for three and seven Data Centers. In our analysis, for three Data Centers we found that minimum Total Response Time is 42.23ms, maximum is 60.25ms and minimum data center processing time is 0.02 ms, maximum is 1.35 ms. For seven data centers we found that minimum Total Response Time is 42.23ms, maximum is 59.93ms and minimum Data Center Processing time is 0.04 ms, maximum is 1.40 ms. KeywordsCloud analyst, Data center (DC), Virtual machines (VM), User bases (UB), Region, load balancing algorithms, service broker policy.

Capacitance Scaling Based Low Power Comparator Design on 28nm FPGA

Reducing the power consumption is the main concern in green computing. So here we used capacitance scaling technique on comparator for optimizing the power. We worked with I/O Power & Leakage Power because Clock Power & Signal Power are independent of capacitance scaling. In our work we have scaled down the capacitance from 512pF to 32pF at various fixed frequency. At 1GHz when we scale down the capacitance from 512pF to 32pF then we got 91.26% reduction in total I/O power dissipation. At 10 GHz when we scale down the capacitance from 512pF to 32pF then we got 91.36% reduction in total I/O power dissipation. At 20 GHz when we scale down the capacitance from 512pF to 32pF then we got 91.364% reduction in total I/O power dissipation. At 30 GHz when we scale down the capacitance from 512pF to 32pF then we got 91.3624% reduction in total I/O power dissipation. At 40GHz when we scale down the capacitance from 512pF to 32pF then we got 91.36277% reduction in total I/O power dissipation. This design is implemented on 28 nm Artix7 FPGA.

High Performance FIFO Design for Processor through Voltage Scaling Technique

Green computing is making revolution by bringing high speed processor with less power consumption. Our paper is based on this philosophy. Objectives: To come out High Performance FIFO for processor by minimizing the power consumption. Methods/Statistical Analysis: To make FPGA based design of FIFO we used voltages and frequency scaling techniques. Keeping voltage constant at 2.3 volt we varied frequency from 20MHz to 250MHz and for other experiment we kept the frequency constant and varies voltages from 1volt to 2.3 volt. Findings: The power consumption is reduced to 95.79% on voltage scaling where as there is a 4.38% less power consumption on frequency scaling. Application/Improvements: It will surely help in futuristic processor development.

Study of phase change technology for computer memory using Se70Te30-xAgx system

The phase change memory is the revolutionary technology for computer world today. Phase change memory alloy is composed of chalcogenide glasses. In the present work Ag is doped in binary Se70Te30 system and activation energy of crystallization is calculated. These ternary alloys are explored in various fields like photo doping, optical imaging, and phase change optical recording. The crystallization kinetics of various ternary Se70Te30-xAgx(x = 0,2,4,6) alloys are studied by using Non-isothermal Iso-Conversional methods. The dependence of activation energy Ec is discussed by various methods. The result shows that the activation energy Ec plays a vital role in proving these materials as best applicable materials in optical phase change recording devices.