Dil muhammed Akbar Hussain

Pseudo open drain IO standards based energy efficient solar charge sensor design on 20nm FPGA

In this paper an approach is made to design Pseudo open drain IO standards Based Energy efficient solar charge sensor design on 20nm and 28nm technology. We have used LVCMOS18, POD10, POD10_DCI and POD12 I/O standard. In this design, we have taken two main parameters for analysis that are frequencies (GHz) and AIRFLOW. We have taken one value for LFM i.e. 250 and Medium as a default profile for heat sink and constant environment. For the simulation of the logic, Xilinx is used with Verilog as hardware description language. We have done our analysis for different frequency values for POD based solar charge inverter. We also observed maximum total power reduction in LVCMOS18 (Artix-7 FPGA) as compared to other I/O standards at 10 GHz. Also there is maximum total power reduction in POD12 (Ultra Scale Kintex) as compared to other I/O standards at 2 GHz. There is also a significant change in device static, I/O power and Clock Power.

Voltage Scalling Based Traffic Light Controller Design on Virtex-7 FPGA Family

Polymer blend becomes one of the effective methods in the development of polymer industries. By applying this technique, it can help to control the environment and create new material with better performance from a net polymer. PP and ABS are the most extensively used commodity polymer due to their good mechanical properties. The aim of this study is to identify the injection molding parameters of PP and ABS such as melt temperature, mold temperature, injection pressure and holding pressure and is to inspect the mechanical properties of hybrid material between ABS and PP such as tensile strength, tensile modulus, and elongation. The relationship between the control parameters and the output response for the hybrid material has also been determined. The samples of PP/ABS blends were prepared via injection molding and have been categorized based on weight percentage. The parameter setting was selected based on the data available in the literature and suggested from resin supplier which is mold temperature, melt temperature, injection and holding pressure. The results showed that with the addition of ABS, the tensile stress is reduced causing the material becomes brittle. With the increasing content of ABS in PP/ABS blends, the tensile modulus will increase while the percentage of elongation in PP/ABS blends decreased. Holding pressure was the most significant effects for tensile strength in PP/ABS blends found from Signal to Noise Ratio (S/N) in the Taguchi Method.

Ship attitude prediction based on Input Delay Neural Network and measurements of gyroscopes

Due to the uncertainty and random nature of ocean waves, the accurate prediction of ship attitude is hard to be achieved, especially in high sea states. A ship attitude prediction method using Input Delay Neural Network (IDNN) is proposed in this paper. One of the advantages of this method is that it takes the measurements of Microelectromechanical Systems (MEMS) gyrosocpes, besides ship Euler angles, as the inputs of IDNN, which can greatly increase the prediction precision of ship attitude with little increase in system cost. The effectiveness of proposed method is validated through a data set sampled in a ship simulation hardware system. Moreover, the factors that affect the prediction performance are also explored through a set of experiments. The prediction method proposed can achieve high precision, that is, the root-mean-square prediction errors for roll, pitch and yaw, are 0.26 deg, 0.12 deg and 0.26 deg, respectively, when the prediction time is 2 sec. This precision is high enough for most attitude stabilization control systems.

High Performance and Energy Efficient Traffic Light Controller Design Using FPGA

In this work, Verilog is used as hardware description language for implementation of traffic light controller. It shows Red, Green and Yellow color at a predefined interval. Technology scaling is used as energy efficient technique. We have used 90nm, 65nm, 40nm and 28nm technology based FPGA and then we have analyzed power consumption for traffic light controller on different FPGA. Leakage power is in range of 97.5-99% of total power consumption by traffic light controller on Virtex-7 FPGA. Signal power, clock power and IOs power are almost negligible. Power dissipation is measured on XPOWER simulator.

SSTL based thermal and power efficient RAM design on 28nm FPGA for spacecraft

In this paper, an approach is made to design a Thermal and Power efficient RAM for that reason we have used DDR4L memory and six different members of SSTL I/Os standards on 28nm technology. Every spacecraft requires most energy efficient electronic system and for that very purpose we have designed the most energy efficient RAM. In this design, we have taken two main parameters for analysis that is frequency (1600 MHz) and Voltage (1.05V). DDR4L operates at the lowest Voltage compared to available RAMs. Environment (LFM, Heat Sink, and Capacitance) is kept constant. For the simulation of the logic, Xilinx is used with Verilog as hardware description language. We have done our analysis with different I/O standards for DDR4L RAM. When we scale down from 288.15K to 348.15K there is maximum total power reduction in SSTL135_R as compared to all considered I/O standards. When we compared different members of SSTL for different temperatures and I/O power we observed maximum thermal efficiency in SSTL135_R at minimum and maximum temperature as compared to all other considered I/O standards. When we scale down from 348.15K to 288.15K there is no power reduction in Clock power, Logic power, Signal power, BRAMs and I/Os power respectively.

Junction Temperature Aware Energy Efficient Router Design on FPGA

Energy, Power and efficiency are very much related to each other. To make any system efficient, Power consumed by it must be minimized or we can say that power dissipation should be less. In our research we tried to make a energy efficient router design on FPGA by varying junction temperature. By varying junction temperature the value of leakage is observed and its effect on total power dissipated is also obtained. This research is made by keeping output load at value 50.The result is also obtained at different frequencies i.e. at 10MHz, 0.1GHz and 1GHz. Different values of output power at observed and reduction the power is calculated accordingly. So this project gives an overview to make the router efficient by varying junction temperature. KeywordsFPGA, Power, Router, Junction Temperature, Energy Efficiency