Abhijit M. Abhyankar

A 2.5Gbps Quad CMOS Transceiver Cell Using Regulated Supply Low Jitter PLL

A 2.5 Gbps serial link is fabricated in TSMC 90nm process. The link is targeted to support various serial link standards. To maintain a constant transmit swing the link supports automatic calibration for the on die termination (ODT) and bias, which supplies the driver. The self biased (Maneatis, 1996) regulated PLL dual loop architecture based on (Kun Yung Ken Chang et al., 2003) is used which minimizes the clock jitter. A replica compensated regulator (Alon et al., 2006) is used in the PLL which cancels both the high frequency and low frequency components of the noise without affecting the PLL loop stability. A clock and data recovery circuits based on 2times over sampling (Alexander, 1975) is implemented inside each individual lane of the serial link. The cell consumes 350mW at 2.5Gbps with transmitted jitter of 44.5ps pk-pk