Craig E. Hampel

Improving Power and Data Efficiency with Threaded Memory Modules

The technique of module-threading utilizes standard DDR DRAM components to build modified memory modules. These modified modules incorporate one or more additional control signals. The modification permits the module to operate at higher performance levels and at lower power levels than standard modules. The modified modules are also capable of finer granularity transactions while still operating at full bandwidth.

Cryptographically Secure On-Chip Firewalling

As SoCs have become more complex, on-chip interconnect has transformed into the point of integration for a variety of system level functions, including security. Integrators have begun to rely on distributed access control hardware to protect resources that are shared between IP cores executing both trusted and untrusted software. Existing solutions cover enforcement of on-chip access control policies but they don’t secure the programming interface nor the hardware against possible attacks. As the embedded content increases in theft value, the on-chip access enforcement will need to consider both software and hardware directed attacks. We introduce a secure on-chip access device that enables secure and programmable allocation of resources in an SoC by offering cryptographically signed programming, fault detection and key integrity. Synthesis results are shown in both ASIC and FPGA implementations.

Do superconducting processors really need cryogenic memories?: the case for cold DRAM

Cryogenic, superconducting digital processors offer the promise of greatly reduced operating power for server-class computing systems. This is due to the exceptionally low energy per operation of Single Flux Quantum circuits built from Josephson junction devices operating at the temperature of 4 Kelvin. Unfortunately, no suitable same-temperature memory technology yet exists to complement these SFQ logic technologies. Possible memory technologies are in the early stages of development but will take years to reach the cost per bit and capacity capabilities of current semiconductor memory. We discuss the pros and cons of four alternative memory architectures that could be coupled to SFQ-based processors. Our feasibility studies indicate that cold memories built from CMOS DRAM and operating at 77K can support superconducting processors at low cost-per-bit, and that they can do so today.