James A. Gasbarro

A 500-megabyte/s data-rate 4.5 M DRAM

A 512-kb*9 DRAM with a 500-Mbyte/s data transfer rate was developed. This high data rate was achieved by designing a DRAM core with a very high internal column bandwidth, and coupling this core with a block-oriented, small-swing, synchronous interface that uses skew-canceling clocks. The DRAM has a 1-kbyte*2-line sense-amp cache and is assembled in a 32-pin vertical surface-mount-type plastic package. The measurement results clearly verified the 500-Mbyte/s data rate. >

PLL design for a 500 MB/s interface

When operating pins at high data rates, the key problem is to control timing skews (both on- and off-chip) so data on the pins can be read in a short time. The problem of external skews is solved by a clocking scheme where clock and data signals travel the same distance between the sender and receiver so that there is little skew on the 600-mV/sub pp/ external signals. There are two clocks: one for incoming data (RxClk) and one for outgoing data (TxClk). A PLL (phase-locked loop) generates the properly skewed internal clocks to operate the bus. The PLL consists of one main loop and two fine loops (one each for the receive and transmit clocks). The main loop is a VCO (voltage-controlled oscillator) based second-order loop using a 6-stage, small-swing, differential ring oscillator VCO. It is locked to the incoming RxClk after it is amplified to full CMOS levels. VCO and input clock frequency are halved to allow the phase/frequency detector more time to settle. The fine loop delays the internal clock (relative to the input RxClk) by an amount that causes the sampler to produce high and low outputs with precisely equal frequency, thereby compensating for sampler setup time.<<ETX>>

Integrated pin electronics for VLSI functional testers

A fully integrated approach is presented for building the pin electronics portion of a VLSI functional tester. The system implements the output vector timing and formatting functions, as well as the input sampling and comparison operations. A computer-controlled feedback loop is employed to obtain a timing accuracy of better than 1 ns. Novel circuit designs are shown which make the circuit suitable for fabrication in a high-density MOS technology. An experimental chip using these techniques was fabricated in 2- mu m CMOS technology and functioned at over 30 megavectors per second. >

500 Mbyte/sec data-rate 512 Kbits*9 DRAM using a novel I/O interface

A novel 512-kb*9 DRAM with a 500-Mbyte/s data transfer rate has been designed. This high data-rate has been achieved by coupling a very high internal column bandwidth DRAM core with a very high internal column bandwidth, and coupling this core with a block oriented, small-swing, synchronous interface that uses skew canceling clocks. The DRAM has a 1-kbyte*2 line sense amplifier cache. This DRAM is assembled in a 32-pin vertical surface mount type plastic package.<<ETX>>

A single-chip, functional tester for VLSI circuits

A single-chip functional tester for VLSI circuits that integrates the vector memory, the error memory, a decompressor, and 16 sets of independently controlled pin electronics on a 9.0*9.4-mm chip is described. The device contains over 200 K transistors and is fabricated using a 1.6- mu m CMOS technology. The integrated pin electronics support a per-pin tester architecture, allowing the transitions for each pin to be independently adjusted to better than 1 ns. The chip dissipates less than 0.75 W running at 25 M vectors/s. By integrating all tester functions on a single chip, it is possible to build all extremely compact tester. A 256-pin tester requires only 16 chips. This size makes it possible to reduce the length of the transmission line between the device under test and the tester to under 10 cm, minimizing signal reflections and enabling the delivery of high-fidelity waveforms.<<ETX>>

Techniques for characterizing DRAMs with a 500 MHz interface

The advent of high-bandwidth DRAMs poses a number of new challenges for test and characterization. This paper describes a collection of techniques that were used in the design and characterization of a new DRAM architecture with 500 MHz I/O signals. Methods of fixturing and calibration are presented for achieving system accuracies of better than 100 ps. Laboratory techniques for measuring critical circuit parameters such as path delay, clock jitter, current source strength, and pin capacitances are shown as well. These techniques, along with on-chip test logic, which allows the DRAM core to be tested using conventional low-speed memory test equipment, enable full characterization of high bandwidth memories.

Testing high speed DRAMs

If test of high speed DRAMs poses a new challenge for test engineers and test makers, then it would seem that the Rambus DRAMs, which have the fastest pin bandwidth of any DRAM in the world, would present the greatest challenge of all. However, at Rambus we have devised a test strategy that minimizes added test cost by allowing our devices to co-exist with the standard manufacturing flow of conventional pagemode devices. Two features have been added to the DRAM logic to facilitate our test strategy. First, a special test mode is incorporated into the Rambus interface that allows direct access to the core from the device pins. This mode provides a simple RAS/CAS-like access mechanism that can be used by existing equipment to exercise the core. Second, a PLL bypass mechanism is incorporated that allows the protocol logic to be functionally tested at low speed. These features allow the device to be tested with conventional low and medium speed memory testers. The only change to the test flow comes at final test.