Abhishek Tomar

A low-glitch and small-logic-area Fibonacci Series DAC

A novel Digital-to-Analog Converter (DAC) utilizing Fibonacci Series is presented in this paper. The ratios of successive weights are smaller than those of binary DAC and larger than those of unary DAC. The features of the proposed DAC are lower glitch-energy than a binary DAC and the number of logic gates is less than a unary DAC. In the proposed DAC in 0.18µm CMOS process, the glitch-energy of the proposed DAC can be reduced by 75% compared to that of binary DAC, and the number of logic gates can be achieved an around 42% reduction compared to that of the unary DAC. We fabricated a prototype 6-bit Fibonacci Series DAC in order to confirm the operation.

Development of low power DAC with pseudo Fibonacci sequence

A 12-bit Digital-analog converter (DAC) with pseudo Fibonacci sequence was fabricated in a 0.18µm CMOS technology. Proposed 12-bit DAC is composed of a 6-bit pseudo Fibonacci sequence and 6bit unary sequence. The power consumption of the proposed DAC is expected lower than that of conventional binary and unary DAC. The simulated power consumption of proposed 12-bit DAC is 40mV at 3.3V supply voltage. Also we fabricated the prototype 6-bit DAC with pseudo Fibonacci sequence and tested. The measured power consumption is very low and almost the same value as a simulated value.

Digitally controlled ring oscillator using fraction-based series optimization for inductorless reconfigurable all-digital PLL

Design and implementation of a CMOS multiphase 10b digitally controlled oscillator (DCO) in ring topology that employs fraction-based series to optimize the transistors size, are presented. One of the advantages of using fraction-based series is that it can reduce the power consumption compared to the binary series without any cost of tuning range and phase noise. The proposed DCO, which was implemented on 0.18 µm CMOS technology, features the tuning frequency 600 MHz to 4.27 GHz with power consumption from 10 mW–40 mW. The measured phase noise is −114.7 dBc/Hz (@4 MHz offset) of the carrier frequency 2.75 GHz.

Low-Phase-Noise, High Switching Speed Digitally Controlled Ring Oscillator in 0.18 µm Complementary Metal Oxide Semiconductor

In this paper a 14-bit digitally controlled oscillator (DCO) with operating frequency up to 4.2 GHz in 0.18 µm complementary metal oxide semiconductor (CMOS) technology is presented. To improve the phase noise, digital control is used that avoids continuous conduction of transistors and controlling transistors operate either in triode or cutoff region. The circuit uses multiple-loop feed forward architecture to increase the switching speed. The DCO has a wide frequency tuning range from 490 MHz to 4.2 GHz. The measured phase noise of the DCO is -121.2 dBc/Hz at a 4-MHz offset from a 3.86-GHz center frequency and power consumption of 48 mW. Due to the phase noise reduction and high switching speed, the DCO has a -164.1 dBc/Hz figure of merit (FOM) that is an improvement of -4 dBc/Hz over the previously published results in the same technology. The chip area is 300×300 µm2.

Low phase noise high switching ring VCO with quadrature output

In this paper, novel two loop architecture of ring type voltage controlled oscillator (VCO) with low phase noise and low power dissipation in 0.18 µm CMOS technology is presented. To reduce phase noise and power dissipation, transistors in sub-feedback loop are operated in linear and cut off region and transistors in main loop of inverter are designed for fast switching with large voltage swing to minimize the switching current. The VCO has a frequency tuning range from 2.40 to 3.45GHz. The simulated result shows a phase noise of −107.56 dBc/Hz @ 1MHz offset from 2.6 GHz center frequency with a power consumption of 32 mW.

Design of digitally controlled LC oscillator with wide tuning range in 0.18um TSMC CMOS technology

Digitally controlled LC oscillator (LC-DCO) design in 0.18 mum CMOS technology is presented with low phase noise and low power dissipation. Particular attention is given to achieve the wide tuning range. A varactor array is implemented using new logic, which made the significant reduction in the number of signal lines and the reduction in the size of local decoder, used to decode the input control word. This decoding scheme reduces the size of parasitic capacitance and power dissipation and provides wide tuning range of the proposed DCO.