Adeel Bajwa

Assembly and Packaging Technologies for High-Temperature and High-Power GaN Devices

This paper gives a detailed analysis on the assembly and packaging technologies for the state-of-the-art GaN-based high-electron-mobility transistors, which are suitable for high-temperature and high-power applications. Silver sintering and transient liquid phase bonding were selected as die-attachment techniques, and gold and palladium were investigated for electrical interconnection materials. Both the die-attachments were characterized for their high-temperature stability up to 450 °C. Systematic electrical characterizations were performed from on-wafer measurements to the final assembly. The thermal and thermomechanical influences of the assembly were assessed. For die-attachments and interconnections, passive temperature shock cycling and active power cycling were performed as an initial attempt to characterize the assembly reliability. Finally, a complete package along with the base plate was proposed, which can survive high temperatures up to 480 °C.

Process optimization and characterization of a novel micro-scaled silver sintering paste as a die-attach material for high temperature high power semiconductor devices

In this study, silver sintering is used as a die-attach technique for the high temperature high power semiconductor devices. Process optimization and characterization of a novel micro-scaled silver sintering paste were performed. The metallurgical aspects on the substrate and die-backside were studied and their influence on the sintering process was evaluated. The influence of degrading mechanisms, such as interfacial diffusion and CTE mismatch on packaging process, was studied and improvements were made. The stresses induced by the assembly process were analyzed analytically and by optical investigation techniques such as white light interferometery and electronic speckle pattern interferometery. Silver sintering can be a potential candidate as a die-attachment technique for future high temperature high power semiconductor devices.

Assembly and packaging technologies for high-temperature and high-power GaN HEMTs

In this work, assembly and packaging technologies for high-temperature high-power GaN high electron mobility transistors (HEMTs) are presented. GaN HEMTs with epitaxial growth on Silicon substrates were used during these experiments. Both die-attachment and interconnection techniques were investigated and a performance comparison is given before and after the assembly process. State-of-the-art silver sintering and transient liquid phase bonding were used as die-attachment methods [2], [3]. For the die-attach material, various characterizations such as shear strength, Energy Dispersive X-ray (EDX) spectroscopy and Differential Scanning Calorimetery (DSC) were performed to characterize the operation up to 500 °C. An estimation of the thermal behavior of the sintered and TLP-bonded GaN HEMTs is performed. For interconnection, gold- and palladium-based materials were investigated for wire-bonding. The complete bonding process was characterized. Estimations about the current carrying capabilities are made for both materials. Passive temperature cycling from -40 to +150 °C was performed as an indication of initial reliability for both die-attachments and interconnections. A systematic electrical characterization of HEMTs is performed starting from the on-wafer measurements up to the final assembly process. The influence of thermal effects on the electrical properties, such as on-state reIn this work, assembly and packaging technologies for high-temperature high-power GaN high electron mobility transistors (HEMTs) are presented. GaN HEMTs with epitaxial growth on Silicon substrates were used during these experiments. Both die-attachment and interconnection techniques were investigated and a performance comparison is given before and after the assembly process. State-of-the-art silver sintering and transient liquid phase bonding were used as die-attachment methods. For the die-attach material, various characterizations such as shear strength, Energy Dispersive X-ray (EDX) spectroscopy and Differential Scanning Calorimetry (DSC) were performed to characterize the operation up to 500 °C. An estimation of the thermal behavior of the sintered and TLP-bonded GaN HEMTs is performed. For interconnection, gold- and palladium-based materials were investigated for wire-bonding. The complete bonding process was characterized. Estimations about the current carrying capabilities are made for both materials. Passive temperature cycling from -40 to +150 °C was performed as an indication of initial reliability for both die-attachments and interconnections. A systematic electrical characterization of HEMTs is performed starting from the on-wafer measurements up to the final assembly process. The influence of thermal effects on the electrical properties, such as on-state resistance at higher power levels, i.e., 350 W were studied before and after the assembly process. A combination of sintered device with the gold wire bonds is considered as the optimum packaging of GaN HEMTs.sistance at higher power levels, i.e., 350 W were studied before and after the assembly process. A combination of sintered device with the gold wire bonds is considered as the optimum packaging of GaN HEMTs.

Heterogeneous Integration at Fine Pitch (≤ 10 µm) Using Thermal Compression Bonding

The scaling of package and circuit board dimensions is central to heterogeneous system integration. We describe our solderless direct metal-to-metal low pressure ( 20 MPa. The combined reduction of dielet interconnect pitch, dielet-to-dielet spacing and trace pitch will enable a Moores law for packaging.

Comparison of new die-attachment technologies for power electronic assemblies

Recently, different die-attachment technologies for power modules such as electrically conductive gluing, silver sintering and transient liquid phase bonding have been investigated as alternatives to soldering. In this paper a comparison of these three die-attach technologies is given. For each an overview of the manufacturing process, as well as key performance parameters like thermal resistance and shear strength are presented. In addition the influence of temperature shock cycles on the modules is investigated. Overall, this work showed that all three die-attachment techniques can be alternatives to replace soldering in specific assembly types of power electronic devices.

Die-attachment technologies for high-temperature applications of Si and SiC-based power devices

In this work, die-attachment technologies for Si and SiC-based power devices are presented, which are suitable for high-temperature applications. Commercially available SiC Schottky diodes were used for the tests. State-of-the-art silver sintering and transient liquid phase bonding along with conductive adhesive technology were used as die-attachment methods. For interconnection, a novel aluminum alloy (AlX) was used. A performance comparison of the aforementioned die-attach technologies was made. Various characterizations such as shear strength, thermal resistances etc. were made for each die-attach material. The diode assemblies were electrically characterized with respect to forward IV-curves and maximum current capabilities. Passive temperature cycling from -40 to +150 °C and active power cycling with various junction temperature differences ΔTj were performed. An estimation of initial reliability is presented for these die-attach technologies.

Integrated neural interfaces

Electronic interfaces to the nervous system are increasingly important for experimental neuroscience as well as medical diagnostics and therapies. Existing neural interfaces are limited, however, by the use of passive recording and stimulation devices that are connected to active electronics on separate physical platforms through large amounts of passive wiring. This manuscript proposes a new approach to integrate active electronics directly with neural recording and stimulation devices using state-of-the-art silicon processing, assembly, and packaging techniques. System concepts are described for fully wireless operation as well as wireline interfacing through FDA-cleared implantable leads and connectors. The approach offers a more modular paradigm of neural interface design, which is greatly needed as the demand for higher channel counts grows.

Latency, Bandwidth and Power Benefits of the SuperCHIPS Integration Scheme

In this paper, we describe the performance and power benefits of our Fine Pitch integration scheme on a Silicon Interconnect Fabric (Si IF). Here we propose a Simple Universal Parallel intERface (SuperCHIPS) protocol enabled by fine pitch dielet to interconnect fabric assembly. We show the dramatic improvements in bandwidth, latency, and power are achievable through our integration scheme where small dielets (1-25 mm2) are attached to a rigid Silicon Interconnect Fabric (Si-IF) at fine interconnect pitch (2-10 μm) and short inter-die distance (50-500 μm) using solderless metal-to-metal thermal compression bonding (TCB). Our simulations show that links in the Si-IF with short wire-lengths (5-25x improvement in data bandwidth. This can improve system performance (>20x) when compared to PCB-style integration and may even approach single die SoC metrics in some cases. Furthermore our protocol is simple and non-proprietary. We show that this scheme enables heterogeneous system integration using a dielet based assembly method and provides significant reduction in design and validation cost.System-level analysis of heterogeneous integration scheme promises power benefits of more than 15% even for very small systems.

Low temperature metal-metal bonding for heterogeneous integration and performance scaling

Au-Au based interconnect bonding (and Cu-Cu bonding) is advanced by addressing the roles of initial surface roughness, chemical mechanical polishing, bonding pressure and temperature. Focused ion beam sectioning through the bonded interface is used to determine grain growth, void evolution, and void faceting.

Characterization of interfacial morphology of low temperature, low pressure Au–Au thermocompression bonding

M.S. Goorsky1,4, K. Schjølberg-Henriksen2, B. Beekley1, T. Bai1, K. Mani1, P. Ambhore1,4, A. Bajwa1,4, N. Malik3 and S.S. Iyer,1,4 1Materials Science and Engineering, University of California, Los Angeles. 90095, USA 2SINTEF ICT, P.O. Box 314 Blindern, 0314 Oslo, Norway 3Centre for Materials Science and Nanotechnology, University of Oslo, 0316 Oslo, Norway 4Center for Heterogeneous Integration and Performance Scaling, University of California, Los Angeles. 90095, USA