Boris Vaisband

Thermal conduction path analysis in 3-D ICs

The on-going effort of integrating heterogeneous circuits as well as the increasing length of global interconnect are driving the semiconductor community towards 3-D integrated circuits. In this work, thermal paths within a 3-D stack are investigated using the HotSpot simulator, and the results are compared to experimental data of a fabricated two layer stack with a single back metal layer. Resistive heaters and sensors measure the heat flow in both the horizontal and vertical dimensions. The dependence of the thermal conductivity on temperature is integrated into the thermal simulation process. At high temperatures (~ 80°C), this effect is responsible for inaccuracies in the temperature and thermal resistance of up to, respectively, 20% and 28%. As confirmed by simulation, those horizontal paths that lie mostly within the silicon layer conduct more heat as compared to the vertical paths, since the thermal conductivity of silicon dioxide is ~ 200 times smaller than the thermal conductivity of silicon.

Experimental Analysis of Thermal Coupling in 3-D Integrated Circuits

A 3-D test circuit examining thermal propagation within a through-silicon via-based 3-D integrated stack has been designed, fabricated, and tested. Design insight into thermal coupling in 3-D integrated circuits (ICs) through both experiment and simulation is provided, and suggestions to mitigate thermal effects in 3-D ICs are offered. Two wafers are vertically bonded to form a 3-D stack. Intraplane and interplane thermal coupling is investigated through single-point heat generation using resistive thermal heaters and temperature monitoring through four-point resistive measurements. Thermal paths are identified and analyzed based on the metric of thermal resistance per unit length. The peak steady-state temperature due to die location within a 3-D stack is described. The reduction in peak temperature through fan-based active cooling is also reported. Thermal propagation from a heat source located on the backside of the silicon is examined with both back metal and on-chip thermal sensors. A comparison of thermal coupling between two different heat sources on the same device plane is also provided.

Hexagonal TSV Bundle Topology for 3-D ICs

Through-substrate vias (TSVs) are key for enabling 3-D integrated circuits (ICs). A hexagonal topology for TSV bundles in 3-D ICs is introduced in this brief. The topology exhibits superior symmetry as compared to the standard mesh topology. A comparison between the hexagonal and mesh topologies in terms of area per TSV, capacitive coupling, effective inductance, and shielding characteristics is offered. The hexagonal topology exhibits a reduction of 13% and 7% in, respectively, area per TSV and capacitive coupling. In addition, a two- to three-orders-of-magnitude decrease in effective inductance within the hexagonal topology is observed.

Noise Coupling Models in Heterogeneous 3-D ICs

Models of coupling noise from an aggressor module to a victim module by way of through silicon vias (TSVs) within heterogeneous 3-D integrated circuits (ICs) are presented in this paper. Existing TSV models are enhanced for different substrate materials within heterogeneous 3-D ICs. Each model is adapted to each substrate material according to the local noise coupling characteristics. The 3-D noise coupling system is evaluated for isolation efficiency over frequencies of up to 100 GHz. Isolation improvement techniques, such as reducing the ground network inductance and increasing the distance between the aggressor and victim modules, are quantified in terms of noise improvements. A maximum improvement of 73.5 dB for different ground network impedances and a difference of 38.5 dB in isolation efficiency for greater separation between the aggressor and victim modules are demonstrated. Compact, accurate, and computationally efficient models are extracted from the transfer function for each of the heterogeneous substrate materials. The reduced transfer functions are used to explore different manufacturing and design parameters to evaluate coupling noise across multiple 3-D planes.

3-D floorplanning algorithm to minimize thermal interactions

An algorithm for including relative thermal interactions among different circuit modules within a 3-D system is introduced in this paper. Application of the proposed algorithm on MCNC and GSRC benchmark circuits is presented. The thermal behavior of a heterogeneous 3-D structure, consisting of a different number of modules and substrate materials, is evaluated to emulate the heat transfer characteristics of practical heterogeneous 3-D systems. The algorithm lowers thermal interactions between different modules while maintaining the peak temperature within a practical range. The thermal characteristics of the floorplan are evaluated using HotSpot and HotSpot Detailed 3-D and compared to a random floorplan. The recorded peak temperatures are within the practical range of on-chip temperatures.

Heterogeneous 3-D ICs as a platform for hybrid energy harvesting in IoT systems

Abstract Three-dimensional integrated circuits are a natural platform for IoT systems. IoT systems exhibit a small footprint, integrate disparate technologies, and require long term sustainability (extremely low power or self-powered). A hybrid energy harvesting system within a three-dimensional integrated circuit is proposed in this paper. The harvesting system exploits different types of energy available from the ambient (electromagnetic, solar, thermal, and kinetic). Integration of the hybrid harvesting system onto a three-dimensional platform ensures that each type of harvested energy can be individually collected. Both static and dynamic evaluations of a hybrid energy harvesting system are provided. For an example IoT system, the static power requirements are approximately 85% of the power delivered to the load. In the dynamic evaluation, a range of activity factors characterizing the load and different storage capacitors are considered. The power requirements of a typical IoT system are shown to be satisfied by a hybrid energy harvesting system within a 3-D platform.

Hybrid energy harvesting in 3-D IC IoT devices

Three-dimensional integrated circuits are a natural platform for IoT devices. IoT devices exhibit a small footprint, integrate disparate technologies, and require long term sustainability (extremely low power or self powered). A hybrid energy harvesting system within a three-dimensional integrated circuit is proposed in this paper. The harvesting system exploits different types of energy available from the ambient (electromagnetic, solar, thermal, and kinetic). Integration of the hybrid harvesting system onto a three-dimensional platform ensures that each type of harvested energy can be individually optimized. In addition, lower parasitic impedances are exhibited within the three-dimensional structure, leading to improved efficiencies in the energy harvesting process. For an example IoT system, the power requirements are less than 57% of the power delivered to the load.

Layer ordering to minimize TSVs in heterogeneous 3-D ICs

A layer ordering algorithm to minimize the total number of TSVs within heterogeneous 3-D integrated circuits is described in this paper. Different constraints may complicate the process of ordering the layers within a 3-D system. These constraints are (1) any two layers must be adjacent, (2) a layer must be placed at a specific location, and (3) a layer must be separated from another layer(s). The algorithm generates an optimal layer order given the number of I/Os among all layers. Certain layers can be pre-assigned to specific locations within the 3-D structure. The application of the algorithm to multiple layer 3-D structures significantly reduces the number of TSVs and occupied area as compared to a random layer assignment. The area overhead of a random solution as compared to the optimal solution for unconstrained 3-D systems (without pre-assigned layers) with three to ten layers is, respectively, ∼24,090 μm2 to ∼854,469 μm2. In constrained 3-D systems (with pre-assigned layers), the area overhead for an eight layer 3-D system with one to six assigned layers ranges up to ∼249, 240 μm2.