Rami Ahola

A single-chip CMOS transceiver for 802.11a/b/g wireless LANs

A dual-band trimode radio fully compliant with the IEEE 802.11a, b, and g standards is implemented in a 0.18-/spl mu/m CMOS process and packaged in a 48-pin QFN package. The transceiver achieves a receiver noise figure of 4.9/5.6 dB for the 2.4-GHz/5-GHz bands, respectively, and a transmit error vector magnitude (EVM) of 2.5% for both bands. The transmit output power is digitally controlled, allowing per-packet power control as required by the forthcoming 802.11 h standard. A quadrature accuracy of 0.3/spl deg/ in phase and 0.05 dB in amplitude is achieved through careful analysis and design of the I/Q generation parts of the local oscillator. The local oscillators achieve a total integrated phase noise of better than -34 dBc. Compatibility with multiple baseband chips is ensured by flexible interfaces toward the A/D and D/A converters, as well as a calibration scheme not requiring any baseband support. The chip passes /spl plusmn/2 kV human body model ESD testing on all pins, including the RF pins. The total die area is 12 mm/sup 2/. The power consumption is 207 mW in the receive mode and 247 mW in the transmit mode using a 1.8-V supply.

A single chip CMOS transceiver for 802.11 a/b/g WLANs

A 0.18 /spl mu/m dual-band tri-mode CMOS radio, fully compliant with the IEEE 802.11 a/b/g standards, achieves a system noise figure of 5.2/5.6 dB (high gain), and an EVM of 2.7/3.0% for the 2.4/5 GHz bands, respectively. Die area is 12 mm/sup 2/, and power consumption is 200 mW in RX and 240 mW in TX using a 1.8 V supply.

A 1.76-GHz 22.6-mW /spl Delta//spl Sigma/ fractional-n frequency synthesizer

A /spl Delta//spl Sigma/ fractional-N frequency synthesizer for the 2-GHz-range wireless communication applications is implemented in a 0.35-/spl mu/m BiCMOS process, using only CMOS components. The synthesizer achieves a close-in phase noise of -81 dBc/Hz, while the spurious tones are at -85 dBc. The synthesizer features a multiple-modulus prescaler employing the phase-switching architecture to minimize the power dissipation. The entire prescaler, including the gigahertz-speed first stages, is implemented using full-swing logic. The current source structure employed in the charge pump provides a constant output current over a wide, almost rail-to-rail output voltage range. The power dissipation of the synthesizer chip is 22.6 mW from a 2.7-V supply.

Bluetooth transceiver design and simulation with VHDL-AMS

This article describes the design challenges of BlueTraC/sup TM/, a low-cost, low-power radio transceiver, and the usage of mixed-signal/mixed-mode techniques and behavioral modeling with ADVance MS (ADMS) from Mentor Graphics to address and solve them. BlueTraC from Spirea is a Bluetooth 1.1-compliant Class 2 radio transceiver. In addition to all the required RF and analog functions, the chip also includes a complete digital GFSK modem, making it a very complex mixed-signal (MS) system-on-chip (SOC). VHDL-AMS, the mixed-signal IEEE 1076.1 standard modeling language, was used to describe the SoC building blocks at different levels of detail and complexity. This permitted us to perform top-level functional verification and debugging as well as detailed subsystem simulations throughout the design process. We will present the concept and the results we obtained in terms of performance and accuracy. The methodology that we deployed increased the confidence in silicon success and allowed on-time delivery.

A novel phase detector with no dead zone and a chargepump with very wide output voltage range

This paper discusses the effects of the so-called dead zone in the phase detector on the phase-noise behavior of phase-locked loop frequency synthesizers. A novel phase detector that completely overcomes the dead zone problem is introduced. Also, a chargepump with a very wide output voltage range is presented. This chargepump allows the use of a VCO with a wider tuning range and, thus, also a lower noise sensitivity. Measurement results that verify the proper operation of these blocks are also presented.

Bluetooth Transceiver Design with VHDL-AMS

This paper describes the design challenges of BlueTraC/spl trade/, a low-cost, low-power radio transceiver and the usage of mixed-signal/mixed-mode techniques and behavioral modeling with ADVance MS (ADMS) from Mentor Graphics to address and solve them. BlueTraC/spl trade/ from Spirea is a Bluetooth 1.1 compliant class 2 radio transceiver. In addition to all the required RF and analog functions, the chip also includes a complete digital GFSK modem, making it a very complex mixed-signal (MS) system-on-chip (SoC). VHDL-AMS, the mixed-signal IEEE 1076.1 standard modeling language, was used to describe the SoC building blocks at different levels of detail and complexity. This permitted us to perform top level functional verification and debugging, as well as detailed subsystem simulations throughout the design process. We present the concept and the results we obtained, in terms of performance and accuracy. The methodology that we deployed increased the confidence in silicon success and allowed on time delivery.

A 2 GHz Phase-Locked Loop Frequency Synthesizer with On-Chip VCO

This paper discusses the implementation of the building blocks for a 2 GHz phase-locked loop frequency synthesizer in a standard 0.5 μm BiCMOS process. These blocks include a low-power optimized dual modulus prescaler which is able to operate with input frequencies up to 2.7 GHz, a phase detector with extremely constant gain throughout the input phase difference range, a chargepump with a rail-to-rail output, and an on-chip voltage-controlled oscillator.

Design of a fully integrated 2 GHz CMOS frequency synthesizer

This paper describes the design of a fully integrated phase-locked loop frequency synthesizer intended for use as the local oscillator in a mobile telecommunication receiver or transmitter. The design of some key blocks is discussed in more detail. These include a 64/65 dual modulus prescaler having a maximum input frequency of 2.4 GHz and a power dissipation of 7.3 mW, 10-bit programmable dividers for VCO and crystal reference frequencies, a phase detector and a chargepump, an integrated passive loop filter, and a balanced voltage-controlled oscillator having a tuning range from 1.8 to 2.2 GHz.

A phase detector with no dead zone and a very wide output voltage range chargepump

This paper discusses the effects of the so-called dead zone in the phase detector on the phase-noise behavior of phase-locked loop frequency synthesizers. A novel phase detector that completely overcomes the dead zone problem is introduced. Also, a chargepump with a very wide output voltage range is presented. This chargepump allows the use of a VCO with a wider tuning range and, thus, also a lower noise sensitivity. Measurement results that verify the proper operation of these blocks are also presented.

A 4 GHz CMOS multiple modulus prescaler

This paper discusses the design of a multiple modulus prescaler for 4 GHz frequency range in a 0.35 /spl mu/m CMOS process. The presented multiple modulus prescaler is especially useful in fractional-N phase-locked loop frequency synthesizers, but the design can also easily be reduced to a dual modulus prescaler commonly used in integer-N synthesizers. Operating from a single 2.7 V supply, the prescaler consumes 10 mA current at an input frequency of 4 GHz.