Adesh Garg

A 500 mW ADC-Based CMOS AFE With Digital Calibration for 10 Gb/s Serial Links Over KR-Backplane and Multimode Fiber

This paper presents the design of an analog-front-end (AFE) integrated into a DSP-based transceiver for both serial 10 Gbps KR-backplane and long-reach-multimode-fiber (LRM) applications. The receiver consists of a programmable gain amplifier (PGA) and a 6-bit 4-way time-interleaved ADC, which is digitally calibrated to compensate for the offset, gain and phase mismatches between the interleaved channels. With a 5 GHz input signal, the ADC achieves overall SNDR of 29 dB, while the measured SNDR of flash sub-ADC is 31.6 dB. The power efficiency FoM of the complete interleaved ADC is 1.4 pJ per conversion step. The PLL uses a calibrated LC-VCO and the TX features a full-rate 3-tap de-emphasis at the output. Inductively tuned buffers connected in tandem are employed to distribute the 10 GHz clock. Random and deterministic jitter measured at the TX output are 0.38 psrms and 2.65 pspp, respectively. Implemented in 65 nm CMOS technology, the AFE occupies an area of 3 mm2 and consumes 500 mW from a 1 V supply. BER of less than 10-15 is measured over legacy backplanes with 26 dB loss at Nyquist and the measured transceiver optical sensitivity is less than -13 dBm for all four LRM stressors, exceeding both the KR and the LRM specifications.

20.2 A 16TX/16RX 60GHz 802.11ad chipset with single coaxial interface and polarization diversity

The IEEE 802.11ad standard supports PHY rates up to 6.7 Gbps on four 2 GHz-wide channels from 57 to 64 GHz. A 60 GHz system offers higher throughput than existing 802.11ac solutions but has several challenges for high-volume production including: integration in the host platform, automated test, and high link loss due to blockage and polarization mismatch. This paper presents a 802.11ad radio chipset capable of SC and OFDM modulation using a 16TX-16RX beamforming RF front-end, complete with an antenna array that supports polarization diversity. To aid low-cost integration in PC platforms, a single coaxial cable interface is used between chips. The chipset is capable of maintaining a link of 4.6 Gbps (PHY rate) at 10 m.

21.7 A 500mW digitally calibrated AFE in 65nm CMOS for 10Gb/s Serial links over backplane and multimode fiber

The demand for bandwidth has fueled the deployment of 10Gb/s traffic over legacy data links such as serial backplanes (10GBase-KR) and multimode fiber (10GBase-MMF) which were originally intended for much lower data rates [1,2]. Under severe channel impairments, a DSP-based transceiver provides robust performance and enables power/area scaling with processes [3–5]. This work describes a 65nm CMOS AFE integrated in a DSP-based PHY for 10Gb/s KR/MMF applications.

A 195mW / 55mW dual-path receiver AFE for multistandard 8.5-to-11.5 Gb/s serial links in 40nm CMOS

Demand for bandwidth in metro networks and data centers has fueled the deployment of 10Gb/s traffic over legacy data links, such as backplanes (KR) and multimode fiber (MMF) [1]. Under severe channel impairments, an ADC-based receiver with a DSP backend provides robust performance, especially for MMF applications, due to the complexity of the channel pulse response and the dynamic nature of the channel impairment. The reach of the backplane channels can also be extended, providing flexibility for system design. Applications such as 10G SFP+ DAC have less channel loss; consequently, a slicer-based binary receiver is a more viable low-power solution. This work describes the AFE of a dual-path receiver that uses both an ADC path and a slicer path for 10Gb/s multi-standard applications in 40nm CMOS.

A 40 nm CMOS 195 mW/55 mW Dual-Path Receiver AFE for Multi-Standard 8.5–11.5 Gb/s Serial Links

This paper presents the design of a power- and area-efficient, high-performance dual-path receiver analog front-end (AFE) for wide multistandard applications of 8.5-11.5 Gb/s, such as 10GBASE-LRM, 10GBASE-KR, 10GBASE-CX1, and 10GBASE-LR/SR. A common programmable gain amplifier (PGA) with programmable peaking is followed by ADC-based and slicer-based paths. The ADC-based path employs a low-power, 6-bit 10 Gs/s, 4X time-interleaved, low BER rectified flash 10 Gs/s ADC that is digitally calibrated to compensate for offset, gain, and phase mismatches between the interleaved channels. The ADC-based receiver with transmitter can compensate for up to a 34 dB insertion loss at 5 GHz Nyquist frequency for a copper backplane channel (10GBASE-KR). The ADC-based receiver can achieve greater than 6 dB margin for three 10GBASE-LRM stressors and dynamic channels. The ADC Figure of Merit (FoM) is a 0.59 pJ/conversion-step for a 5 GHz input at a 10.3125 GHz clock rate. The slicer-based path uses a continuous-time linear equalizer (CTLE) after high linear PGA to provide 10 dB total equalization at 5 GHz Nyquist frequency for 10GBASE-SR application. Its measured input sensitivity of 30 mVppd and high-frequency jitter tolerance of 0.35 UIpp with 0.7 UIpp total input jitter well exceed specifications in the standard. The receiver AFE occupies 0.82 mm 2 and consumes 195 mW for ADC path and 55 mW for slicer path in a 40 nm standard CMOS process.

11.3 Gbps CMOS SONET Compliant Transceiver for Both RZ and NRZ Applications

In this paper, an 11.3 Gbps CMOS SONET compliant transceiver designed to work in both RZ and NRZ data formats is presented. Using a configurable high-speed transmit path utilizing an AND gate and a duty cycle adjustment circuit, the transmitter can switch output format between RZ and NRZ. The TX driver exhibits 17 ps rise/fall times, 0.25 psrms RJ, and 2 pspp DJ. In RZ mode, TX output duty cycle can be adjusted within 40-60% range. To improve input sensitivity in both RZ and NRZ reception, the receiver incorporates a limiting amplifier with a distributed threshold adjustment circuit. It achieves 5 mVpp-diff RX input sensitivity with 0.54 UI high-frequency jitter tolerance. An adaptation scheme based on nested linear search is implemented to control the distributed threshold adjustment circuit. While demonstrating the integration of RZ/NRZ functionality into a single-chip solution using 65 nm CMOS technology, the transceiver core occupies 1.36 mm2 and consumes 214 mW.

A quad-channel 112–128 Gb/s coherent transmitter in 40 nm CMOS

A quad-channel, 112-128 Gb/s coherent DP-QPSK transmitter in 40 nm CMOS is presented. The 27.9-32.1 Gb/s TX features a half-rate architecture with a 2-tap FIR. The measured output has an amplitude of 1.2Vpp-diff with 1.3 ps deterministic jitter (DJ). The DP-QPSK TXs precoded data alignment is maintained through the quad-lane transmitter by the use of an automatic synchronous feedback loop, removing the need for a master global reset. The PLL outputs the full-rate and half-rate clock with ±0.5 UI skew adjustment relative to the data. The power consumption of the transmitter and PLL is 712 mW.

2.2 A 780mW 4×28Gb/s transceiver for 100GbE gearbox PHY in 40nm CMOS

Network traffic speeds are increasing to meet the demands of data centers and network operators to support data-rich services like video streaming and social media. This has accelerated the adoption of 100Gb/s connectivity from the present 10Gb/s and 40Gb/s rates. One challenge that remains is the high power consumption of 100Gb/s systems. As mentioned in [1], power dissipation of the 100GbE gearbox transceiver is a significant portion of the optical module power. This paper demonstrates a low-power quad-lane 20-to-28Gb/s transceiver targeting 100GbE/40GbE (IEEE 802.3ba) standard. The transceiver features a low-jitter TX, half-rate calibrated RX slicer with folded active inductor and a wide-range PLL (20 to 28GHz) with low-power half-rate clock driver using programmable distributed inductors. It operates from a standard 0.9V supply and the power consumption for line-side transceiver is 780mW for 28Gb/s. Additionally the chipset integrates a system interface that is CAUI-compliant, composed of a 10-lane data bus operating at 9.95 to 11.2Gb/s. In default mode it converts 100GbE (10×10 Gb/s) signal to a 4×25Gb/s line signal and vice versa. The line-side interface can also be reconfigured as 40GbE, with both line- and system-side operating at 4×11.2Gb/s.