Namik Kocaman

A 500 mW ADC-Based CMOS AFE With Digital Calibration for 10 Gb/s Serial Links Over KR-Backplane and Multimode Fiber

This paper presents the design of an analog-front-end (AFE) integrated into a DSP-based transceiver for both serial 10 Gbps KR-backplane and long-reach-multimode-fiber (LRM) applications. The receiver consists of a programmable gain amplifier (PGA) and a 6-bit 4-way time-interleaved ADC, which is digitally calibrated to compensate for the offset, gain and phase mismatches between the interleaved channels. With a 5 GHz input signal, the ADC achieves overall SNDR of 29 dB, while the measured SNDR of flash sub-ADC is 31.6 dB. The power efficiency FoM of the complete interleaved ADC is 1.4 pJ per conversion step. The PLL uses a calibrated LC-VCO and the TX features a full-rate 3-tap de-emphasis at the output. Inductively tuned buffers connected in tandem are employed to distribute the 10 GHz clock. Random and deterministic jitter measured at the TX output are 0.38 psrms and 2.65 pspp, respectively. Implemented in 65 nm CMOS technology, the AFE occupies an area of 3 mm2 and consumes 500 mW from a 1 V supply. BER of less than 10-15 is measured over legacy backplanes with 26 dB loss at Nyquist and the measured transceiver optical sensitivity is less than -13 dBm for all four LRM stressors, exceeding both the KR and the LRM specifications.

20.2 A 16TX/16RX 60GHz 802.11ad chipset with single coaxial interface and polarization diversity

The IEEE 802.11ad standard supports PHY rates up to 6.7 Gbps on four 2 GHz-wide channels from 57 to 64 GHz. A 60 GHz system offers higher throughput than existing 802.11ac solutions but has several challenges for high-volume production including: integration in the host platform, automated test, and high link loss due to blockage and polarization mismatch. This paper presents a 802.11ad radio chipset capable of SC and OFDM modulation using a 16TX-16RX beamforming RF front-end, complete with an antenna array that supports polarization diversity. To aid low-cost integration in PC platforms, a single coaxial cable interface is used between chips. The chipset is capable of maintaining a link of 4.6 Gbps (PHY rate) at 10 m.

21.7 A 500mW digitally calibrated AFE in 65nm CMOS for 10Gb/s Serial links over backplane and multimode fiber

The demand for bandwidth has fueled the deployment of 10Gb/s traffic over legacy data links such as serial backplanes (10GBase-KR) and multimode fiber (10GBase-MMF) which were originally intended for much lower data rates [1,2]. Under severe channel impairments, a DSP-based transceiver provides robust performance and enables power/area scaling with processes [3–5]. This work describes a 65nm CMOS AFE integrated in a DSP-based PHY for 10Gb/s KR/MMF applications.

A Fully Integrated 10-Gb/s Receiver With Adaptive Optical Dispersion Equalizer in 0.13-

A 10 Gb/s receiver, containing an adaptive equalizer, a clock and data recovery, and a de-multiplexer, is implemented in 0.13-mum CMOS. The chip is intended for long-haul optical fiber links where chromatic and polarization mode dispersions are reach-limiting factors. The equalization is performed by a continuous time filter and a two-tap decision feedback equalizer while automatic threshold and phase adjustments are embedded in the CDR. Use of an analog equalizer with digital adaptation garners total power dissipation of 950 mW. Error-free operation over 200 km of single mode fiber is demonstrated. With 140 km of single mode fiber, optical signal to noise ratio penalty is only 2dB. Differential group delay of 100 ps can also be tolerated

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An 8.5-11.5Gbps SONET transceiver with a referenceless CDR employing an algorithmic frequency acquisition scheme (without using any training sequence) is designed in a 65nm digital CMOS process. A modified digital quadricorrelator frequency detector (M-DQFD) is incorporated into an LC-based VCO coarse tuning adjustment. The transceiver complies with stringent SONET OC-192 jitter requirements. Within a 400μs acquisition time, the RX achieves a high-frequency jitter tolerance of 0.58UIpp at 10mVpp-diff input sensitivity. The TX serial output exhibits a random jitter (RJ) of 205fs (rms). The transceiver occupies 0.97mm2 and consumes 141mA at 1.0V.

CMOS

Demand for bandwidth in metro networks and data centers has fueled the deployment of 10Gb/s traffic over legacy data links, such as backplanes (KR) and multimode fiber (MMF) [1]. Under severe channel impairments, an ADC-based receiver with a DSP backend provides robust performance, especially for MMF applications, due to the complexity of the channel pulse response and the dynamic nature of the channel impairment. The reach of the backplane channels can also be extended, providing flexibility for system design. Applications such as 10G SFP+ DAC have less channel loss; consequently, a slicer-based binary receiver is a more viable low-power solution. This work describes the AFE of a dual-path receiver that uses both an ADC path and a slicer path for 10Gb/s multi-standard applications in 40nm CMOS.

An 8.5–11.5-Gbps SONET Transceiver With Referenceless Frequency Acquisition

This paper presents a quad-lane serial transceiver that supports virtually all data center communication standards around 8.5-13 Gbps, implemented in 28 nm CMOS technology. The transmitter consists of 20:2 mux followed by a half-rate source-series terminated (SST) driver embedded with a 4 tap FFE and an analog equalizer. The receiver has an adaptive CTLE, 5 tap DFE, and fully digital CDR followed by 2:20 demux. At 13 Gbps, the transceiver can equalize 35 dB Nyquist loss at BER of 10-12. At 1.0 V supply, the transceiver consumes 49 mW/lane at 13 Gbps rate with full equalization capability. An LC VCO-based fractional PLL provides the clocking to quad TX/RX lanes using a low-power inductively tuned clock routing channel. The transceiver architecture not only enables the baud rate operation from 8.5 to 13 Gbps but also supports a wide range of oversampled subrates. This work represents the lowest reported power in its class to date, and the transceiver is suitable for many applications due to its comprehensive flexibility and power efficiency.

A 195mW / 55mW dual-path receiver AFE for multistandard 8.5-to-11.5 Gb/s serial links in 40nm CMOS

An 8.0 GHz to 12.2 GHz PLL with a capacitor multiplier-based active loop filter is designed in a 28 nm digital CMOS process. A passive loop filter-based version of the PLL is also implemented for comparison. While the PLL area is comparable to that of digital PLLs, the PLL performance is as good as that of an analog PLL that employs a passive loop filter. The capacitor multiplier-based active loop filter PLL has a jitter performance of 198 fs (rms), while its passive loop filter-based counterpart shows a jitter performance of 195 fs (rms). The PLL occupies 0.093 mm2 and consumes 15.5 mA at 1.0V.

A 3.8 mW/Gbps Quad-Channel 8.5–13 Gbps Serial Link With a 5 Tap DFE and a 4 Tap Transmit FFE in 28 nm CMOS

A 10Gbps receiver, containing an adaptive equalizer, a clock and data recovery (CDR), and a demultiplexer, is implemented in 0.13 mum CMOS. By compensating for optical dispersion, this chip recovers transmitted data after 200km of single-mode fiber at BER < 10-12 . Use of analog equalizer with digital adaptation garners total power dissipation of 950mW

A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications

This paper presents the design of a power- and area-efficient, high-performance dual-path receiver analog front-end (AFE) for wide multistandard applications of 8.5-11.5 Gb/s, such as 10GBASE-LRM, 10GBASE-KR, 10GBASE-CX1, and 10GBASE-LR/SR. A common programmable gain amplifier (PGA) with programmable peaking is followed by ADC-based and slicer-based paths. The ADC-based path employs a low-power, 6-bit 10 Gs/s, 4X time-interleaved, low BER rectified flash 10 Gs/s ADC that is digitally calibrated to compensate for offset, gain, and phase mismatches between the interleaved channels. The ADC-based receiver with transmitter can compensate for up to a 34 dB insertion loss at 5 GHz Nyquist frequency for a copper backplane channel (10GBASE-KR). The ADC-based receiver can achieve greater than 6 dB margin for three 10GBASE-LRM stressors and dynamic channels. The ADC Figure of Merit (FoM) is a 0.59 pJ/conversion-step for a 5 GHz input at a 10.3125 GHz clock rate. The slicer-based path uses a continuous-time linear equalizer (CTLE) after high linear PGA to provide 10 dB total equalization at 5 GHz Nyquist frequency for 10GBASE-SR application. Its measured input sensitivity of 30 mVppd and high-frequency jitter tolerance of 0.35 UIpp with 0.7 UIpp total input jitter well exceed specifications in the standard. The receiver AFE occupies 0.82 mm 2 and consumes 195 mW for ADC path and 55 mW for slicer path in a 40 nm standard CMOS process.