Bharath Raghavan

A 500 mW ADC-Based CMOS AFE With Digital Calibration for 10 Gb/s Serial Links Over KR-Backplane and Multimode Fiber

This paper presents the design of an analog-front-end (AFE) integrated into a DSP-based transceiver for both serial 10 Gbps KR-backplane and long-reach-multimode-fiber (LRM) applications. The receiver consists of a programmable gain amplifier (PGA) and a 6-bit 4-way time-interleaved ADC, which is digitally calibrated to compensate for the offset, gain and phase mismatches between the interleaved channels. With a 5 GHz input signal, the ADC achieves overall SNDR of 29 dB, while the measured SNDR of flash sub-ADC is 31.6 dB. The power efficiency FoM of the complete interleaved ADC is 1.4 pJ per conversion step. The PLL uses a calibrated LC-VCO and the TX features a full-rate 3-tap de-emphasis at the output. Inductively tuned buffers connected in tandem are employed to distribute the 10 GHz clock. Random and deterministic jitter measured at the TX output are 0.38 psrms and 2.65 pspp, respectively. Implemented in 65 nm CMOS technology, the AFE occupies an area of 3 mm2 and consumes 500 mW from a 1 V supply. BER of less than 10-15 is measured over legacy backplanes with 26 dB loss at Nyquist and the measured transceiver optical sensitivity is less than -13 dBm for all four LRM stressors, exceeding both the KR and the LRM specifications.

21.7 A 500mW digitally calibrated AFE in 65nm CMOS for 10Gb/s Serial links over backplane and multimode fiber

The demand for bandwidth has fueled the deployment of 10Gb/s traffic over legacy data links such as serial backplanes (10GBase-KR) and multimode fiber (10GBase-MMF) which were originally intended for much lower data rates [1,2]. Under severe channel impairments, a DSP-based transceiver provides robust performance and enables power/area scaling with processes [3–5]. This work describes a 65nm CMOS AFE integrated in a DSP-based PHY for 10Gb/s KR/MMF applications.

A 780 mW 4 × 28 Gb/s Transceiver for 100 GbE Gearbox PHY in 40 nm CMOS.

This paper describes a reconfigurable 4 × 28 Gb/s transceiver supporting 100 GbE/40 GbE standards. In each lane, the transmitter incorporates a 3-tap FIR with independent output phase adjustment, and the receiver has a half-rate CDR with a dedicated eye-monitor channel. There is a global resonant clock distribution network implemented using programmable distributed on-chip inductors. Implemented in a 40 nm CMOS process, the TX output measures 1.87 pspp DJ and 202 fsrms RJ. The RX jitter tolerance is 0.46 UIpp at 80 MHz with an input sensitivity of 27 mVpp-diff. The transceiver achieves BER on a channel with 20 dB loss at Nyquist, dissipating only 780 mW from a 0.9 V supply for all four lanes at 28 Gb/s operation.

A Sub-2 W 39.8–44.6 Gb/s Transmitter and Receiver Chipset With SFI-5.2 Interface in 40 nm CMOS

The introduction of 40Gb/s networks, spurred by 40Gb/s WDM growth, can alleviate bandwidth bottlenecks of Internet infrastructure while simultaneously reducing operating costs. Increasingly, standard CMOS technology is used to enable transceiver speeds [1-5] previously achievable only by using expensive bipolar technology. However, at 40Gb/s, limited channel bandwidth coupled with stringent receiver jitter tolerance requirements demands better solutions than exist currently.

A Dual-Channel 23-Gbps CMOS Transmitter/Receiver Chipset for 40-Gbps RZ-DQPSK and CS-RZ-DQPSK Optical Transmission

This paper describes a dual-channel 23 (20 to 27) Gbps chipset designed in a 40-nm CMOS process for 40 Gbps differential quadrature phase-shift keying (DQPSK) optical transmission. The transmitter has a 2-tap FIR filter and generates two channels of full-rate data. Data outputs exhibit 10 ps rise/fall times, 0.2 psrms RJ, 0.8 pspp DJ, and a ±0.5 UI skew adjustment relative to the full-rate and half-rate clock outputs. The receiver has two 20-27-Gbps input channels, with each channel including a peaking filter, decision threshold adjustment, and 1-tap loop-unrolled DFE. It achieves a 7- mVppd input sensitivity and a 0.7-UIpp high-frequency jitter tolerance. The transmitter and receiver dissipate 0.63 and 1.2 W, respectively.

A dual 23Gb/s CMOS transmitter/receiver chipset for 40Gb/s RZ-DQPSK and CS-RZ-DQPSK optical transmission

This paper presents the first CMOS dual bitrate chipset with equalization in transmitter and receiver as well as a clock to data skew adjustment. Both the transmitter and the receiver consume less power than those in previously published results in the works of Hosida et al. (2007).

11.3 Gbps CMOS SONET Compliant Transceiver for Both RZ and NRZ Applications

In this paper, an 11.3 Gbps CMOS SONET compliant transceiver designed to work in both RZ and NRZ data formats is presented. Using a configurable high-speed transmit path utilizing an AND gate and a duty cycle adjustment circuit, the transmitter can switch output format between RZ and NRZ. The TX driver exhibits 17 ps rise/fall times, 0.25 psrms RJ, and 2 pspp DJ. In RZ mode, TX output duty cycle can be adjusted within 40-60% range. To improve input sensitivity in both RZ and NRZ reception, the receiver incorporates a limiting amplifier with a distributed threshold adjustment circuit. It achieves 5 mVpp-diff RX input sensitivity with 0.54 UI high-frequency jitter tolerance. An adaptation scheme based on nested linear search is implemented to control the distributed threshold adjustment circuit. While demonstrating the integration of RZ/NRZ functionality into a single-chip solution using 65 nm CMOS technology, the transceiver core occupies 1.36 mm2 and consumes 214 mW.

A 125 mW 8.5–11.5 Gb/s serial link transceiver with a dual path 6-bit ADC/5-tap DFE receiver and a 4-tap FFE transmitter in 28 nm CMOS

This paper describes an 8.5-11.5 Gb/s transceiver with a dual path receiver and a voltage-mode transmitter. The RX can operate either in ADC mode for complex loss channels such as optical multimode fiber or in DFE mode for copper-based backplane links. The ADC path implements a 2X interleaved 6-bit rectifying flash ADC using a programmable gain amplifier (PGA) with controlled bandwidth and peaking, comparator pipelining, and super-source follower circuit techniques. The LRM optical sensitivity requirements are met with a > 6 dB margin while achieving an ENOB of 4.59 bits at a 5 GHz input frequency. The TX/RX DFE path achieves copper channel loss compensation of 38 dB with BER <; 10-12 at 11.5 Gb/s consuming 46mW from a 0.9V supply. The TX/RX ADC path consumes 125 mW at 10.3125 Gb/s. The TX/RX occupies 0.56 mm2 in a 28nm standard CMOS process.

2.2 A 780mW 4×28Gb/s transceiver for 100GbE gearbox PHY in 40nm CMOS

Network traffic speeds are increasing to meet the demands of data centers and network operators to support data-rich services like video streaming and social media. This has accelerated the adoption of 100Gb/s connectivity from the present 10Gb/s and 40Gb/s rates. One challenge that remains is the high power consumption of 100Gb/s systems. As mentioned in [1], power dissipation of the 100GbE gearbox transceiver is a significant portion of the optical module power. This paper demonstrates a low-power quad-lane 20-to-28Gb/s transceiver targeting 100GbE/40GbE (IEEE 802.3ba) standard. The transceiver features a low-jitter TX, half-rate calibrated RX slicer with folded active inductor and a wide-range PLL (20 to 28GHz) with low-power half-rate clock driver using programmable distributed inductors. It operates from a standard 0.9V supply and the power consumption for line-side transceiver is 780mW for 28Gb/s. Additionally the chipset integrates a system interface that is CAUI-compliant, composed of a 10-lane data bus operating at 9.95 to 11.2Gb/s. In default mode it converts 100GbE (10×10 Gb/s) signal to a 4×25Gb/s line signal and vice versa. The line-side interface can also be reconfigured as 40GbE, with both line- and system-side operating at 4×11.2Gb/s.