Adrian M. Ionescu

Tunnel field-effect transistors as energy-efficient electronic switches

Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in todays integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal–oxide–semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

Double-Gate Tunnel FET With High-

In this paper, we propose and validate a novel design for a double-gate tunnel field-effect transistor (DG tunnel FET), for which the simulations show significant improvements compared with single-gate devices using a gate dielectric. For the first time, DG tunnel FET devices, which are using a high-gate dielectric, are explored using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average subthreshold swing of 57 mV/dec, and a minimum point slope of 11 mV/dec. The 2D nature of tunnel FET current flow is studied, demonstrating that the current is not confined to a channel at the gate-dielectric surface. When varying temperature, tunnel FETs with a high-kappa gate dielectric have a smaller threshold voltage shift than those using SiO2, while the subthreshold slope for fixed values of Vg remains nearly unchanged, in contrast with the traditional MOSFET. Moreover, an Ion/Ioff ratio of more than 2 times 1011 is shown for simulated devices with a gate length (over the intrinsic region) of 50 nm, which indicates that the tunnel FET is a promising candidate to achieve better-than-ITRS low-standby-power switch performance.

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Reference NANOLAB-CONF-2005-019View record in Web of Science Record created on 2007-05-16, modified on 2017-05-10

Gate Dielectric

In this letter, we report that the source and channel Fermi-Dirac distributions in interband-tunneling-controlled transistors play a fundamental role on the modulation of the injected current. We explain the superlinear onset of the output characteristics based on the occupancy function modulation. Thus, we point out that, along with the tunneling barrier transparency, the availability of carriers and empty states, at the beginning and at the end of the tunneling path, respectively, should be always taken into account for a proper modeling of tunnel FETs.

Suspended-gate MOSFET: bringing new MEMS functionality into solid-state MOS transistor

This work reports the first complete experimental demonstration and investigation of subthreshold swing, SS, smaller than 60 mV/decade, at room temperature, due to internal voltage amplification in FETs with a Metal-Ferroelectric-Metal-Oxide gate stack. The investigated p-type MOS transistor is a dedicated test structure to explore the negative capacitance effect by probing the internal voltage between the P(VDF-TrFE) and SiO2 dielectric layers of the gate stack. We find that the region of internal surface potential amplification, dψS/dVg>1, corresponds to an S-shape of the polarization versus ferroelectric voltage (associated with negative capacitance). In Fe-FETs the internal voltage amplification could significantly lower their SS, even without reaching sub-60mV/dec values. SSmin as low as 46 to 58 mV/decade and average swings, SSavg, as small as 51 to 59 mV/dec are observed for the first time in a minor loop hysteretic characteristics of Fe-FETs.

Understanding the Superlinear Onset of Tunnel-FET Output Characteristic

This work reports on the self-heating effect (SHE) characterization of HV DMOSFETs and the accurate extraction of the equivalent thermal impedance of the device (thermal resistance, R/sub TH/, and capacitance, C/sub TH/) needed for advanced device and IC simulation. A simple pulsed-gate experiment is proposed and the influence of its parameters (pulse duration and duty factor) are analysed. It is demonstrated that in our 100 V DMOSFET, SHE is cancelled by using pulses with duration less that 2 /spl mu/s and duty factor lower that 1:100. The new extraction method of device thermal resistance and capacitance exploits analytical modelling and dedicated extraction plots using the measurements of output characteristics at various applied pulses and the gradual reduction of SHE with pulse duration and duty factor. Both R/sub TH/ and C/sub TH/ are assumed and extracted in saturation region as quasi-independent functions of the device bias (injected power) at a given external temperature. We originally report on the temperature dependence of the HV device thermal resistance that is shown to be a linear function of external temperature (in our device, R/sub TH/ could increase by almost 100% over 100/spl deg/C). SPICE simulations with the extracted thermal R/sub TH/-C/sub TH/ circuit are finally used to fully validate the proposed method.This letter reports on the self-heating effect (SHE) characterization of high-voltage (HV) DMOSFETs and the accurate extraction of the equivalent thermal impedance of the device (thermal resistance, R/sub TH/, and capacitance, C/sub TH/) needed for advanced device and IC simulation. A simple pulsed-gate experiment is proposed and the influence of its parameters (pulse duration and duty factor) are analyzed. It is demonstrated that in our 100 V DMOSFET, SHE is cancelled by using pulses with duration less that 2 /spl mu/s and duty factor lower that 1:100. The new extraction method exploits analytical modeling and dedicated extraction plots for thermal resistance and capacitance using the measurements of output characteristics at various applied pulses and the gradual reduction of SHE with pulse duration and duty factor. Both R/sub TH/ and C/sub TH/ are extracted in saturation region considering their dependence on SHE and external temperature. In DMOSFETs, the thermal resistance is shown to be a significant linear function of the device temperature (in our device, R/sub TH/ could increase by more than 100% over 100/spl deg/C). The thermal capacitance appears to decrease with the injected power and shows a plateau at high V/sub D/. SPICE simulations with the extracted thermal network R/sub TH/-C/sub TH/ circuit are finally used to fully validate the proposed method.

Metal-Ferroelectric-Meta-Oxide-semiconductor field effect transistor with sub-60mV/decade subthreshold swing and internal voltage amplification

The experimental characterization of the surface impedance of monolayer graphene at micro and millimeter wave frequencies is addressed. Monolayer graphene is transferred on a substrate stack, which is placed in the cross-section of a rectangular waveguide. In the fundamental mode, this setup is equivalent to a TE-polarized plane wave impinging under oblique incidence on an infinite graphene sheet, and similarly, the surface impedance of the graphene is a simple lumped element in a transmission-line model, that exactly represents the electromagnetic problem under study. Using this model, we propose a technique based on transmission matrices to accurately extract the surface impedance. The method is able to relax the influence of the substrates tolerances by taking advantage of the graphene infinitesimally small electrical thickness. It can also account for any gap between the sample and the test waveguide, thereby allowing to disregard graphene-metal contact resistance issues. The approach has been success...

Self-heating characterization and extraction method for thermal resistance and capacitance in high voltage MOSFETs

An analytical model for the suspended-gate field-effect transistor (SGFET), dedicated to the dc analysis of SGFET logic circuits, is developed. The model is based on the depletion approximation and expresses the pull-in voltage, the pull-out voltage, and the stable travel range as a function of the structural parameters. Gate position is explicitly expressed as a function of the gate voltage, thus enabling the convenient integration of the analytical SGFET relationships into the standard MOSFET models. Starting from the new SGFET model, the influence of the mechanical hysteresis on the circuit steady-state behavior is discussed, the potential of using the SGFET as an ultra-low power switch is demonstrated, and the operation of the complementary SGFET inverter is analyzed.

Non-contact characterization of graphene surface impedance at micro and millimeter waves

A novel MEMS device architecture: the SOI SG-MOSFET, which combines a solid-state MOS transistor and a suspended metal membrane in a unique metal-over-gate architecture, is proposed. A unified physical analytical model (weak, moderate and strong inversions) is developed and used to investigate main electrostatic characteristics in order to provide first-order design criteria for low-voltage operation and high-performance. It is demonstrated that the use of a thin gate oxide (<20 nm) is essential for a high C/sub on//C/sub off/ ratio (>100) and a low spring constant (<100 N/m) is needed for low voltage (<5 V) actuation. An adapted fabrication process is reported.

Analytical Modeling of the Suspended-Gate FET and Design Insights for Low-Power Logic

In this letter, we present a novel device, the germanium electron-hole (EH) bilayer tunnel field-effect transistor, which exploits carrier tunneling through a bias-induced EH bilayer. The proposed architecture provides a quasi-ideal alignment between the tunneling path and the electric field controlled by the gate. The device principle and performances are studied by 2-D numerical simulations. This device allows interesting features in terms of low operating voltage (<; 0.5 V), due to its super-steep subthreshold slope (SS_AVG ~ 13 mV/dec over six decades of current), I_ON/I_OFF ratio of ~ 10⁹, and drive current of I_ON ~ 10 μA/μm at V_DD = 0.5 V. The same structure with symmetric voltages can be used to achieve a p-type device with I_ON and I_OFF levels comparable to the n-type, which enables a straightforward implementation of complementary logic that could theoretically reach a maximum operating frequency of 1.39 GHz when V_DD = 0.25 V.