D. Bouvet

Influence of nitrogen profile on electrical characteristics of furnace‐ or rapid thermally nitrided silicon dioxide films

Thin silicon dioxide films nitrided in N2O by rapid thermal processing (RTP) or in a classical furnace were investigated by x‐ray photoelectron spectroscopy, secondary ion mass spectroscopy, and electrical measurements on metal‐oxide‐semiconductor capacitors. Differences between the two nitridation processes were observed and explained. In lightly nitrided films, nitrogen occupies two configurations. Nitrogen is bound to three silicon atoms with at least one in the substrate or all three in the oxide. In RTP‐nitrided films, both of these species are confined to within 1.5 nm of the Si/SiO2 interface. In furnace‐nitrided films, the first species is also located close to the interface whereas the second one fills most of the regrown oxide thickness. In furnace‐grown films, which are more heavily nitrided, a third structure due to Si2=N–O is observed throughout the layer. The electrical characteristics are well correlated with the amount of nitrogen at the interface that is bound to Si atoms in the substrate.

Fabrication and Characterization of Gate-All-Around Silicon Nanowires on Bulk Silicon

This paper reports on the top-down fabrication and electrical performance of silicon nanowire (SiNW) gate-all-around (GAA) n-type and p-type MOSFET devices integrated on bulk silicon using a local-silicon-on-insulator (SOI) process. The proposed local-SOI fabrication provides various nanowire cross sections: Omega-like, pentagonal, triangular, and circular, all controlled by isotropic etching using nitride spacers and silicon sacrificial oxidation. The reported top-down SiNW fabrication offers excellent control of wire doping and placement, as well as ohmic source and drain contacts. A particular feature of the process is the buildup of a tensile strain in all suspended nanowires, attaining values of few percents, reflected in stress values higher than 2-3 GPa. A very high yield (>90%) is obtained in terms of functionality of long-channel SiNW GAA mosfet. Device characteristics are reported from cryogenic temperature (T = 5 K) up to 150 degC, and promising characteristics in terms of low-field electron mobility, threshold voltage control, and subthreshold slope are demonstrated. Low field mobility for electrons up to 850 cm2 /Vmiddots is reported at room temperature in suspended devices with triangular cross sections; this mobility enhancement is explained by the process-induced tensile strain. In short, suspended SiNW GAA with small triangular cross sections, a single-electron transistor (SET) operation regime is highlighted at T = 5 K. This is attributed to a combined effect of strain and corner conduction in triangular channel cross sections, suggesting the possibility to hybridize CMOS and SET functions by a unique nanowire fabrication platform.

Demonstration of subthrehold swing smaller than 60mV/decade in Fe-FET with P(VDF-TrFE)/SiO 2 gate stack

This work experimentally demonstrates, for the first time, that by integrating a thin ferroelectric layer into a gate stack of a standard MOS transistor one, it is possible to overcome the 60 mV/decade subthreshold swing limit at room temperature of MOSFET. We find sub-threshold swings as low as 13 mV/decade in Fe-FETs with 40 nm P(VDF-TrFE)/SiO2 gate stack. The mechanism governing the low subthreshold swing in Fe-FET transistors is the negative capacitance of the ferroelectric layer that provides voltage amplification; with our particular ferroelectric gate stack we report for the first time negative capacitance at room temperature.

Ultra-high density carbon nanotubes on Al-Cu for advanced vias

An integration scheme for carbon nanotube via interconnects is described to produce nanotube densities of 2.5 10¹² tubes/cm² or 8 10¹² walls/cm² on metallic Al-Cu lines, an order of magnitude beyond the previous state of art, and, for first time, close to that needed for implementation.

The High-Mobility Bended n-Channel Silicon Nanowire Transistor

This work demonstrates a method for incorporating strain in silicon nanowire gate-all-around (GAA) n-MOSFETs by oxidation-induced bending of the nanowire channel and reports on the resulting improvement in device performance. The variation in strain measured during processing is discussed. The strain profile in silicon nanowires is evaluated by Raman spectroscopy both before device gate stack fabrication (tensile strains of up to 2.5% are measured) and by measurement through the polysilicon gate on completed electrically characterized devices. Drain current boosting in bended n-channels is investigated as a function of the transistor operation regime, and it is shown that the enhancement depends on the effective electrical field. The maximum observed electron mobility enhancement is on the order of 100% for a gate bias near the threshold voltage. Measurements of stress through the full gate stack and experimental device characteristics of the same transistor reveal a stress of 600 MPa and corresponding improvements of the normalized drain current, normalized transconductance, and low-field mobility by 34% (at maximum gate overdrive), 50% (at g max), and 53%, respectively, compared with a reference nonstrained device at room temperature. Finally, it is found that, at low temperatures, the low-field mobility is much higher in bended devices, compared with nonbended devices.

Capacitive nanoelectromechanical switch based on suspended carbon nanotube array

We present the fabrication and high frequency characterization of a capacitive nanoelectromechanical system (NEMS) switch using a dense array of horizontally aligned single-wall carbon nanotubes (CNTs). The nanotubes are directly grown onto metal layers with prepatterned catalysts with horizontal alignment in the gas flow direction. Subsequent wetting-induced compaction by isopropanol increases the nanotube density by one order of magnitude. The actuation voltage of 6 V is low for a NEMS device, and corresponds to CNT arrays with an equivalent Young’s modulus of 4.5–8.5 GPa, and resistivity of under 0.0077 Ω⋅cm. The high frequency characterization shows an isolation of −10 dB at 5 GHz.

Bended Gate-All-Around Nanowire MOSFET: a device with enhanced carrier mobility due to oxidation-induced tensile stress

In this paper we investigate the mobility enhancement due to strain in bended NW MOSFETs. Stress of 200 MPa to 2 GPa, induced by thermal oxidation, is measured in suspended NW FETs by Raman spectroscopy. Mobility enhancement of more than 100% is observed. Performance gain of bended compared to non-bended structures is most pronounced in low field conditions and at low temperatures.

Modeling of the depletion of the amorphous-silicon surface during hemispherical grained silicon formation

A model, based on surface energy minimization under nonequilibrium conditions, is presented to describe the evolution of the amorphous silicon (a-Si) topography near the hemispherical grained silicon. The evolution of the depletion area can be explained by a combination between capture of silicon (Si) atoms at the grain boundary and energy minimization of the surrounding a-Si surface. Grain depletion dependence on annealing time was measured by means of transmission electron microscopy. The simulated results agree well with the real observations. This approach is presented as a first step in physically based modeling of HSG formation.

Transient Off-Current in Junctionless FETs

We report preliminary measurements of transient drain current undershoot with time constants of the order of milliseconds in thick and highly doped n-type junctionless field-effect transistors. This effect might be attributed to a process involving generation of holes in the n-type-doped channel, which can also explain the partial channel depletion as consequence of channel screening by an inversion layer, thus impeding the device to be switched off. The approach described in this work could also be used for characterization of silicon channels in junctionless nanowires.

Retention in nonvolatile silicon transistors with an organic ferroelectric gate

A silicone-based one-transistor nonvolatile memory cell has been implemented by integration of a ferroelectric polymer gate on a standard n-type metal oxide semiconductor field effect transistor. The polarization reversal in the gate results in a stable and reproducible memory effect changing the source-drain current by a factor 102–103, with the retention exceeding 2–3 days. Analysis of the drain current relaxation and time-resolved study of the spontaneous polarization via piezoforce scanning probe microscopy indicates that the retention loss is controlled by the interface-adjacent charge injection rather than the polarization instability. A semiquantitative model describes the time-dependent retention loss characterized by an exponential decay of the open state current of the transistor. The unique combination of properties of the ferroelectric copolymer of vinylidene fluoride and trifluoroethylene, including an adequate spontaneous polarization and low dielectric constant as well as rather benign proc...