Livio Lattanzio

Understanding the Superlinear Onset of Tunnel-FET Output Characteristic

In this letter, we report that the source and channel Fermi-Dirac distributions in interband-tunneling-controlled transistors play a fundamental role on the modulation of the injected current. We explain the superlinear onset of the output characteristics based on the occupancy function modulation. Thus, we point out that, along with the tunneling barrier transparency, the availability of carriers and empty states, at the beginning and at the end of the tunneling path, respectively, should be always taken into account for a proper modeling of tunnel FETs.

Complementary Germanium Electron–Hole Bilayer Tunnel FET for Sub-0.5-V Operation

In this letter, we present a novel device, the germanium electron-hole (EH) bilayer tunnel field-effect transistor, which exploits carrier tunneling through a bias-induced EH bilayer. The proposed architecture provides a quasi-ideal alignment between the tunneling path and the electric field controlled by the gate. The device principle and performances are studied by 2-D numerical simulations. This device allows interesting features in terms of low operating voltage (<; 0.5 V), due to its super-steep subthreshold slope (SS_AVG ~ 13 mV/dec over six decades of current), I_ON/I_OFF ratio of ~ 10⁹, and drive current of I_ON ~ 10 μA/μm at V_DD = 0.5 V. The same structure with symmetric voltages can be used to achieve a p-type device with I_ON and I_OFF levels comparable to the n-type, which enables a straightforward implementation of complementary logic that could theoretically reach a maximum operating frequency of 1.39 GHz when V_DD = 0.25 V.

Electron-hole bilayer tunnel FET for steep subthreshold swing and improved ON current

We propose a novel Tunnel field-effect transistor (TFET) concept called the electron-hole bilayer TFET (EHBTFET). This device exploits the carrier tunneling through a bias-induced electron-hole bilayer in order to achieve improved switching and higher drive currents when compared to a lateral p-i-n junction TFET. The device principle and performances are studied by 2D numerical simulations. Output and transfer characteristics, as well as the impact of back gate bias, silicon thickness and gate length on the device behavior are evaluated. Near ideal average subthreshold slope (SS<inf>AVG</inf> ∼ 12 mV/dec over 6 decades of current) and I<inf>ON</inf>/I<inf>off</inf> > 10⁸ at V<inf>D</inf> = V<inf>G</inf> = 0.5 V figures of merit are obtained, due to the OFF-ON binary transition which leads to the abrupt onset of the band-to-band tunneling inside the silicon channel. Drive current (I<inf>ON</inf>) in the EHBTFET is 3× higher that in traditional all-Si Tunnel FET but below 0.1 μA/μm.

Tunneling and Occupancy Probabilities: How Do They Affect Tunnel-FET Behavior?

In this letter, the occupancy and tunneling probabilities of interband tunneling devices are studied, pointing out the fundamental function of the source Fermi-Dirac distribution. Particularly, the reason for the degraded subthreshold swing, which is typical of devices with highly doped source, is explained, and its relation with the high-energy source Fermi tail is carefully analyzed. Simultaneously, the poor driving capability of Tunnel-FET devices is investigated, highlighting the primary role played by the occupancy functions.

Quantum Mechanical Study of the Germanium Electron–Hole Bilayer Tunnel FET

The electron-hole bilayer tunnel field-effect transistor (EHBTFET) is an electronic switch that uses 2-D-2-D sub-band-to-sub-band tunneling (BTBT) between electron and hole inversion layers and shows significant subthermal swing over several decades of current due to the step-like 2-D density of states behavior. In this paper, EHBTFET has been simulated using a quantum mechanical model. The model results are compared against transactions on computer-aided design simulations and remarkable differences show the importance of quantum effects and dimensionality in this device. Ge EHBTFET with channel thickness of 10 nm results as a promising device for low supply voltage, subthreshold logic applications, with a super steep switching behavior featuring SSavg ~ 40 mV/dec up to VDD. Furthermore, it has been demonstrated that high on current levels ( ~ 40 μA/μm) can be achieved due to the transition from phonon-assisted BTBT to direct BTBT at higher biases.

Tunnel-FET architecture with improved performance due to enhanced gate modulation of the tunneling barrier

The Tunnel-FET (TFET) device is a gated reverse biased p-i-n junction whose working principle is based on the quantum mechanical Band-to-Band Tunneling (B2BT) mechanism [1]. The OFF-ON transition can be much more abrupt than for conventional MOSFETs, thus allowing a reduction of the supply voltage and power consumption in logic applications [2]. Several TFETs with point Subthreshold Swing (SS) lower than 60mV/dec have been experimentally demonstrated with different architectures as conventional single gate Silicon-on-Insulator (SOI), Double Gate (DG) and Gate-All-Around (GAA) [3,4]. Unfortunately in all cases a relatively large average SS and a poor on-current have been observed.

Ferroelectric transistors with improved characteristics at high temperature

We report on the temperature dependence of ferroelectric metal-oxide-semiconductor (MOS) transistors and explain the observed improved characteristics based on the dielectric response of ferroelectric materials close to the Curie temperature. The hysteretic current-voltage static characteristics of a fully depleted silicon-on-insulator transistor, with 40 nm vinylidene fluoride trifluorethylene, and 10 nm SiO2 gate stack, are measured from 300 to 400 K. In contrast with conventional MOS field effect transistors (MOSFETs), the subthreshold swing and the transconductance show, respectively, a minimum and a maximum near the Curie temperature (355 K) of the ferroelectric material. A phenomenological model is proposed based on the Landau-Ginzburg theory. This work demonstrates that a MOSFET with a ferroelectric layer integrated in the gate stack could have nondegraded or even improved subthreshold swing and transconductance at high temperature even though the hysteresis window is reduced. As a consequence, we suggest that for ferroelectric transistors with appropriately designed Curie temperatures, the performance degradation of logic or analog circuits, nowadays operating near 100 degrees C, could be avoided

An innovative band-to-band tunneling analytical model and implications in compact modeling of tunneling-based devices

In this paper, an analytical band-to-band tunneling model is proposed, validated by means of drift-diffusion simulation and comparison with experimental data, implemented in Verilog-A, and finally proven with SPICE simulator through simulation of circuits featuring tunneling diodes. The p-n junction current calculation starts from a non-local Band-to-Band tunneling theory including the electron-phonon interaction and therefore it is particularly suited for indirect semiconductor materials such as silicon- or germanium-based interband tunneling devices.

The Hysteretic Ferroelectric Tunnel FET

We present the fabrication and the electrical characterization of ferroelectric tunnel FETs (Fe-TFETs). This novel family of hysteretic switches combines the low subthreshold power of band-to-band tunneling devices with the retention characteristics of Fe gate stacks, offering some interesting features for future one-transistor (1T) memory cells. We report Ion/Ioff larger than 105 and Ioff on the order of 100 fA/μm in micrometer-scale p-type Fe-TFETs fabricated on ultrathin-film (fully depleted) silicon-on-insulator substrates with a SiO2/Al2O3/ PVDF gate stack processed at low temperature. The hysteretic characteristics of the TFETs with Fe gate stacks are revealed by static experiments, and the principle of the proposed device is further confirmed by 2-D calibrated numerical simulations. Low temperature measurements down to 77 K confirm the reduced sensitivity of the TFET subthreshold swing to temperature and distinguish them from fabricated reference Fe metal-oxide-semiconductor FETs. Finally, we investigate the potential of Fe-TFETs as 1T memory devices and find retention times on the order of a few minutes at room temperature.

Modeling the Temperature Dependence of Fe-FET Static Characteristics Based on Landau's Theory

The performance of a standard MOSFET degrades with the increase in temperature, impacting the power consumption of the device. In this paper, we report the opposite trend, which is reflected in an improvement of main performance factors in ferroelectric FETs (Fe-FETs), when the temperature is increased. We explain our results by Landaus theory, which is also used to develop and validate an analytical model of ferroelectric capacitance. In order to validate the model, we fabricate and dc characterize a fully depleted silicon-on-insulator transistor with 10-nm SiO2 and 40 nm of vinylidene fluoride trifluorethylene P(VDF-TrFE) as a gate stack at different temperatures, ranging from 300 to 400 K. The transconductance and the subthreshold swing of a Fe-FET show a maximum and a minimum in correspondence to the Curie temperature of the ferroelectric, respectively. The proposed model and extraction is valid for any type of ferroelectric materials and Fe-FETs. Finally, this paper demonstrates that the performance degradation in a standard MOSFET (e.g., transconductance and subthreshold swing) at a high temperature of operation could be reduced or even suppressed in a Fe-FET if the Curie temperature of the gate stack is appropriately designed.