Adrian Rusu

More Accurate Models Of The Interfaces Oxide Charge From The Ultra‐Thin SOI Films

An inherent SOI device dedicated for the in situ electrical characterization of wafers is the pseudo‐MOS transistor that easily provides a key parameter: Flat‐Band Voltage, VFB. Usual models for this voltage were established for SOI structures with 0,2μm…2μm film thickness and 0,4…100μm oxide thickness. The classical models of VFB, deduced for micronic sizes, present some deficiencies in the nanodevice area. An interface charge about 1012e/cm2 in micronic sizes means 1e/100nm2 equivalent with one electron per device area in the nano‐domain. This paper analyses the flat‐band voltage modeling, due to the consequences of the down‐scaling of the SOI wafers.

Generalised DC characteristics of gate-controlled diodes in avalanche breakdown regime

This paper considers the gate-controlled diode as a device performing both analog and digital functions. This behavior is encountered in the breakdown regime of the device, where the transfer characteristic has slopes in a wide range, from a cvasilinear to a collapse region. The form of this characteristic depends on the electrode that is considered as reference. Theoretical models and experimental measurements demonstrate these assumptions.

Measurements of the electrical characteristics in DC and AC regime for an epinephrine BOI device

The electrical properties of the chemical mediators at synapses level could be investigated in vitro, with some test biodevices. One of neurotransmitters, like epinephrine, placed on an insulator support and contacted with metal electrodes, provides a Biomaterials On Insulators - BOI-type, structure. The test device is inspired from the pseudo-MOS technique, frequently used in the Silicon On Insulator characterisation. The DC regime study allows some polarography experiments. A behavior like the Field Effect Transistor was also investigated in DC regime, biasing a third terminal - the gate. A gate voltage control on the current is expected. It is still linear, emphasising none inversion layer onset. The AC regime measurements of the BOI device provided some conductometry results, providing the epinphrine resistivity.

MOS saturation model based on channel resistance

Actual MOS transistors models only use empirical models for the variation of the drain current in saturation. This is due to the bidimensional character of the MOS transistor channel. Gradual approximation can no longer be used for the whole transistor analysis due to the channel length modulation. But the gradual approximation still stands for the effective channel length of the transistor. And this gives a good hint to where an analytical model for saturation could have its roots. This paper proposes to present one such analytical model based on experimental data and on a determined constant channel resistance ratio.

Gated diode in breakdown voltage collapse regime — A test vehicle for oxide characterization

A new method for oxide characterization, based on flat-band voltage shift direct measurement is presented. This opportunity appears in the breakdown voltage collapse, for a gated diode operated in the common-cathode configuration. Additionally, the proposed method outfits uniform conditions for voltage drop across the oxide and carrier multiplication.

The drift/diffusion ratio of the MOS transistor drain current

The paper presents a new method to evaluate the ratio between the two components of drain current in MOS transistors: drift and diffusion. By setting certain limits for this ratio, the moderate inversion region can be delimited in transfer electrical characteristics. The limits of the moderate inversion give the possibility for a more accurate applying of the continuous models. Some examples are given by extracting the main model parameters for a sub-micron MOS transistor and the limits of moderate inversion are compared with the results obtained using other models.

The threshold voltage model of a SOI-MOSFET on films with Gaussian profile

The analytical models for electric field and potential distributions are useful for a lot of SOI devices, like SOI-MOSFET, SOI-BJT, three-dimensional device, SOI sensors and the others. For example, they are necessary for establish the inversion or accumulation conditions for front and back interfaces. The paper refers to a one-dimensional analysis, both for partially and fully depleted devices on films with nonuniform doping. The goal of this paper is to obtain an accurate model for the field and the potential distribution in the SOI structures with Gaussian doping concentration of impurities in the film. The results have been used for threshold voltage deduction, but they represent a reference point in developing of new models for SOI-devices fabricated on Gaussian profile films. In the fully depleted films case, the depletion of the silicon substrate for gate voltages that entirely depleted the film was considered. The results were compared with PISCES numerical simulations and were in good agreement.

Common anode amplifier of a commercial MOS transistor in avalanche gated diode configuration

In this paper we present a voltage amplifier using a gated diode in breakdown regime. The diode is biased with a constant current and is in common anode configuration. The measured diode was obtained from a commercial nMOS transistor that has the substrate pin available. The circuit will be analyzed in this paper and the theory is in good agreement with the measurements.

The small signal amplification of the gated diode operated in breakdown regime

In this paper we present a unity-gain follower amplifier based on a gated diode operated in breakdown regime in common cathode configuration. The amplifier has only one stage and it provides power amplification, high input impedance and a low output one. The maximum frequency that can be applied on the entrance of the amplifier so that the output remains undistorted is dependent on the bias current therefore it can be used also as a programmable low pass filter. The diode is fully characterized in order to set the bias in the linear region where the amplification is very close to one.

Carrier mobility and series resistance MOSFET modeling

The scaling-down evolution of semiconductor devices will ultimately attend fundamental limits as transistor reach the nanoscale aria. In this context the MOSFET models must give the process variations and the relevant characteristics like current, conductance, transconductance, capacitances, flicker thermal or high frequency noise and distortion. The new challenge of nanotechnology needs very accurate models for active devices. The design of linear analog circuits lacks models for state-of-the-art MOS transistors to accurately describe distortion effects. This is mainly due to inaccurate modelling of the mobility degradation effect i.e. the dependence of carrier mobility in the inversion layer on the gate normal electric field. For short-channel devices the influence of series resistance becomes important and depends on the gate voltage. The drain current expression incorporating a new mobility relation obtained from quantum mechanical transport analysis and the series resistance influence is in good agreement with experiment.