Constantin Bulucea

Trench DMOS transistor technology for high-current (100 A range) switching

Abstract Design and processing concepts are presented that have led to the development of rugged high-current (100 A range) low-voltage trench DMOS transistors, featuring 4 mΩ on-resistance, with controlled bulk avalanche breakdown at 70 V and gate dielectric breakdown at 60 V. The results of a simulation-based investigation are also presented, revealing that the trench DMOS technology has at least a factor-of-two die area advantage over its planar DMOS counterpart in the range from low (50 V) to medium (200 V) voltages.

The calculation of the avalanche multiplication factor in silicon p—N junctions taking into account the carrier generation (thermal or optical) in the space-charge region

The influence of carrier generation within the space-charge regions of silicon p-n junctions upon their breakdown characteristics is analyzed. Universal plots for the calculation of the total multiplication in one-sided silicon junctions versus voltage and substrate concentration are given, which take into account both injection and generation of initiating carriers. It is shown that the multiplication factor M of practical (i.e., generation-dominated) silicon junctions differs from the pure hole-pure electron multiplication factors M p and M n and ranges between them, i.e., M_{p} . Its calculated voltage dependence is well approximated by Millers relationship with an exponent n between 4 and 7 for impurity concentrations in the substrate between 1014and 1017cm-3.

Recalculation of Irvin's resistivity curves for diffused layers in silicon using updated bulk resistivity data

Abstract A basic subset of Irvins average-resistivity curves for Gaussian and complementary error function profiles is recalculated using the updated resistivity-concentration data available for boron-and phosphorus-doped bulk silicon. The calculations are made under the same physical modeling as originally assumed by Irvin. Differences from the original curves are in the direction of lower resistivity for a given surface and background dopant concentration, and are comparable with those reported for bulk silicon.

Physics, Technology, and Modeling of Complementary Asymmetric MOSFETs

The physics, technology, and modeling of complementary asymmetric MOSFETs are reviewed and illustrated with statistically representative silicon data from a recent manufacturing implementation, in which the transistors for the secondary power supply voltage are offered in asymmetric and symmetric constructions. The in-depth analysis of the device physics of asymmetric transistors provides new insights into their physical operation and into the operation of transistors using halo implants in general. The variability, matching, and noise implications of using halo implants are also analyzed, concluding that both asymmetric and symmetric devices need to be offered for uncompromised circuit design. The challenges associated with the compact modeling the asymmetric transistors are also reviewed and illustrated. The preferred manufacturing implementation uses retrograde wells with no dopant fillers at the surface, while avoiding the drain-to-source punch-through by source-side-only halo implants. In addition to the known switching speed and maximum voltage gain advantages of the asymmetric transistors, this particular device architecture offers superior hot-carrier reliability and transistor design flexibility. The availability of retrograde wells enables construction of high-reliability complementary extended-drain MOSFETs for a third higher power supply voltage.

Monolithic integration of trench vertical DMOS (VDMOS) power transistors into a BCD process

The monolithic integration of trench vertical DMOS (VDMOS) n-channel transistors into an IC BCD process is reported for the first time. The integration scheme for the trench VDMOS module is discussed and silicon results are compared with TCAD simulations. For a 50-V device, the integrated trench device is shown to offer at least a factor-of-two R/sub DS(ON)/ /spl times/ area advantage over its planar counterpart. An R/sub DS(ON)/ /spl times/ area value of 80 m/spl Omega/mm/sup 2/ is achieved for the integrated trench VDMOS using a minimum feature size of 1 /spl mu/m.

On the MOS depletion of a high-level-injection plasma

Abstract Determined by the recent interest in MOS-turn-off thyristors, a simulation-assisted analysis is carried out on the effect of a transversal electric field on the electron-hole plasma generated at high levels of injection, in silicon. Numerical simulations of gate-controlled p + nn + structures show that a plasma-filled channel cannot be depleted by the application of a transversal field. The electron-hole plasma is influenced by the externally applied field for only a distance of two plasma Debye lengths from the surface, which is in the range of 1 … 100 nm, depending on the level of injection, in typical high-voltage devices.

Threshold voltage control in buried-channel MOSFETs

Abstract The analytical calculation of the threshold voltage in the buried-channel MOSFET (BCMOSFET) is revisited in connection with its widespread use in CMOS VLSI electronics. This device class is shown to comprise two distinct varieties, i.e., metallurgical-channel and field-induced-channel, depending on the thickness of the channel layer and the doping levels in the channel and body regions. The threshold voltage equations of the metallurgical-channel variety are reviewed briefly, and a first-order model is derived for the field-induced-channel variety. The long-channel threshold voltage of BCMOSFETs is calculated analytically providing a complete set of practical design equations and plots. The analytical model is validated by 2-D numerical calculations, and also by independent statistical observations on manufacturing data. It enables a clear theoretical assessment of the advantages and limitations of the BCMOSFET device architecture in the context of VLSI miniaturization.

Breakdown voltage of diffused epitaxial junctions

Abstract The quantitative aspects of the breakdown-voltage calculations in reach-through-limited p + − n − n + junctions are revisited, using numerical simulation. It is shown that the conventional abrupt-junction approximation may underestimate the breakdown voltage of diffused epitaxial junctions by as much as 60%, depending on junction depth. Oppositely, but less erroneously, a combined abrupt/linearly-graded approximation overestimates the breakdown voltage by at most 15%. A set of numerically calculated plots are provided for the design of low-voltage power devices.

Field distribution and avalanche breakdown of trench MOS capacitors operated in deep depletion

Two-dimensional electric-field and avalanche breakdown calculations are presented for trench MOS capacitors operated in deep depletion. Breakdown calculations are based on the ionization-integral approach, with field values resulting from solutions of Poissons equation. Plots of breakdown voltage versus background impurity concentration, oxide thickness, and trench width are provided, which are recommended for first-order engineering calculations of semiconductor structures involving the deeply depleted trench capacitor as a breakdown-voltage-setting component. Calculations cover the range of 10/sup 14/ to 10/sup 18/ cm/sup -3/ background impurity concentration and 0.01 to 5 mu m oxide thickness and apply to well-separated (i.e. noninteracting) rectangular trenches with widths equal to or larger than 0.2 mu m. >

Control of emitter current crowding in bipolar junction transistors using laterally-graded base doping profiles

Abstract An advanced bipolar junction transistor structure is proposed and analysed that controls undesirable emitter current crowding, using a laterally-graded base doping profile. The average doping concentration in the base region increases from the emitter centre towards its periphery, making the emitter periphery into a higher-threshold injector than the rest of the active area. Extensive numerical calculations of the steady-state and transient operation of two-section test vehicles using the PISCES-2B two-dimensional simulator have confirmed theoretical expectations. Design trade-offs and potential applications are discussed.