Adrien Vaysset

Spin-Hall assisted magnetic random access memory

We propose a write scheme for perpendicular spin-transfer torque magnetoresistive random-access memory that significantly reduces the required tunnel current density and write energy. A sub-nanosecond in-plane polarized spin current pulse is generated using the spin-Hall effect, disturbing the stable magnetic state. Subsequent switching using out-of-plane polarized spin current becomes highly efficient. Through evaluation of the Landau-Lifshitz-Gilbert equation, we quantitatively assess the viability of this write scheme for a wide range of system parameters. A typical example shows an eight-fold reduction in tunnel current density, corresponding to a fifty-fold reduction in write energy, while maintaining a 1 ns write time.

Design and benchmarking of hybrid CMOS-Spin Wave Device Circuits compared to 10nm CMOS

In this paper, we present a design and benchmarking methodology of Spin Wave Device (SWD) circuits based on micromagnetic modeling. SWD technology is compared against a 10nm FinFET CMOS technology, considering the key metrics of area, delay and power. We show that SWD circuits outperform the 10nm CMOS FinFET equivalents by a large margin. The area-delay-power product (ADPP) of SWD is smaller than CMOS for all benchmarks from 2.5× to 800×. On average, the area of SWD circuits is 3.5× smaller and the power consumption is two orders of magnitude lower compared to the 10nm CMOS reference circuits.

Non-volatile spin wave majority gate at the nanoscale

A spin wave majority fork-like structure with feature size of 40\,nm, is presented and investigated, through micromagnetic simulations. The structure consists of three merging out-of-plane magnetization spin wave buses and four magneto-electric cells serving as three inputs and an output. The information of the logic signals is encoded in the phase of the transmitted spin waves and subsequently stored as direction of magnetization of the magneto-electric cells upon detection. The minimum dimensions of the structure that produce an operational majority gate are identified. For all input combinations, the detection scheme employed manages to capture the majority phase result of the spin wave interference and ignore all reflection effects induced by the geometry of the structure.

Spintronic majority gates

In this paper we present an overview of two types of majority gate devices based on spintronic phenomena. We compare the spin torque majority gate and the spin wave majority gate and describe work on these devices. We discuss operating conditions for the two device concepts, circuit implication and how these reflect on materials choices for device implementation.

Toward error-free scaled spin torque majority gates

The functionality of a cross-shaped Spin Torque Majority Gate is explored by means of micromagnetic simulations. The different input combinations are simulated varying material parameters, current density and size. The main failure mode is identified: above a critical size, a domain wall can be pinned at the center of the cross, preventing further propagation of the information. By simulating several phase diagrams, the key parameters are obtained and the operating condition is deduced. A simple relation between the domain wall width and the size of the Spin Torque Majority Gate determines the working range. Finally, a correlation is found between the energy landscape and the main failure mode. We demonstrate that a macrospin behavior ensures a reliable majority gate operation.

Exchange-driven Magnetic Logic

Direct exchange interaction allows spins to be magnetically ordered. Additionally, it can be an efficient manipulation pathway for low-powered spintronic logic devices. We present a novel logic scheme driven by exchange between two distinct regions in a composite magnetic layer containing a bistable canted magnetization configuration. By applying a magnetic field pulse to the input region, the magnetization state is propagated to the output via spin-to-spin interaction in which the output state is given by the magnetization orientation of the output region. The dependence of this scheme with input field conditions is extensively studied through a wide range of micromagnetic simulations. These results allow different logic operating modes to be extracted from the simulation results, and majority logic is successfully demonstrated.

Operating conditions and stability of spin torque majority gates: Analytical understanding and numerical evidence

The functionality of a cross-shaped Spin Torque Majority Gate (STMG) is primarily limited by the pinning of a domain wall (DW) at the center of the device. Here, an analytical model is built to calculate the conditions for such a pinning and to deduce the operating range. The assumptions of the model and the conclusions are validated by micromagnetic simulations. The total magnetic energy of the DW state is derived. By minimizing this energy with respect to two degrees of freedom, the DW stability condition is obtained. We find that the lateral length of the STMG is the critical dimension: it must be smaller than about five times the DW width. This result is confirmed by micromagnetic simulations with a high accuracy. In process, we solved a more fundamental problem: the macrospin limit of a finite ferromagnet containing one pinning site. We found the correction of the usual DW width expression due to finite length of wires.

Micromagnetic simulations of magnetoelastic spin wave excitation in scaled magnetic waveguides

We study the excitation of spin waves in scaled magnetic waveguides using the magnetoelastic effect. In uniformly magnetized systems, normal strains parallel or perpendicular to the magnetization direction do not lead to spin wave excitation since the magnetoelastic torque is zero. Using micromagnetic simulations, we show that the nonuniformity of the magnetization in submicron waveguides due to the effect of the demagnetizing field leads to the excitation of spin waves for oscillating normal strains both parallel and perpendicular to the magnetization. The excitation by biaxial normal in-plane strain was found to be much more efficient than that by uniaxial normal out-of-plane strain. For narrow waveguides with a width of 200 nm, the excitation efficiency of biaxial normal in-plane strain was comparable to that of shear strain.We study the excitation of spin waves in scaled magnetic waveguides using the magnetoelastic effect. In uniformly magnetized systems, normal strains parallel or perpendicular to the magnetization direction do not lead to spin wave excitation since the magnetoelastic torque is zero. Using micromagnetic simulations, we show that the nonuniformity of the magnetization in submicron waveguides due to the effect of the demagnetizing field leads to the excitation of spin waves for oscillating normal strains both parallel and perpendicular to the magnetization. The excitation by biaxial normal in-plane strain was found to be much more efficient than that by uniaxial normal out-of-plane strain. For narrow waveguides with a width of 200 nm, the excitation efficiency of biaxial normal in-plane strain was comparable to that of shear strain.

Inverter Propagation and Fan-Out Constraints for Beyond-CMOS Majority-Based Technologies

Traditional logic synthesis faces challenges of meeting the requirements demanded by the many emerging nanotech-nologies that are based on logic models different from standard CMOS. Several emerging nanodevices including Quantum-dot Cellular Automata (QCA) and Spin Torque Majority Gates (STMG) are based on majority logic. In addition, technology constraints require to restrict the number of fan-outs or impose difficulties in realizing inversions. In this paper, we use a majority-based logic synthesis approach to synthesize inversion-free networks with restricted fan-out. We propose one algorithm that propagates all inversions to the primary inputs and another algorithm that limits the number of fan-outs of each majority gate. These algorithms show significant impact on QCA- and STMG-based circuits. Experimental results demonstrate that the average area-delay-energy product can be improved by 3.1× in QCA-based circuits and from 2.9× to 8.1× for STMG-based circuits.

Area and routing efficiency of SWD circuits compared to advanced CMOS

In this paper, we present a standard cell design methodology for Spin Wave Device (SWD) circuits. We perform Place and Route (P&R) experiments against a 10nm FinFET CMOS technology and compare the area, the routing and metal distribution of several arithmetic benchmarks. We show that SWD circuits although they require more metal layers than CMOS designs and although they contain double the number of nets, their pin density and net length distribution makes them easier (2× shorter nets) and cheaper (13% less wiring required) to route than CMOS, without impact the area of the designs.