Bart Soree

Direct and Indirect Band-to-Band Tunneling in Germanium-Based TFETs

Germanium is a widely used material for tunnel FETs because of its small band gap and compatibility with silicon. Typically, only the indirect band gap of Ge at 0.66 eV is considered. However, direct band-to-band tunneling (BTBT) in Ge should be included in tunnel FET modeling and simulations since the energy difference between the Ge conduction band edges at the L and Γ valleys is only 0.14 eV at room temperature. In this paper, we theoretically calculate the parameters A and B of Kanes direct and indirect BTBT models at different tunneling directions ([100], [110], and [111]) for Si, Ge and unstrained Si1-xGex. We highlight how the direct BTBT component becomes more important as the Ge mole fraction increases. The calculation of the band-to-band generation rate in the uniform electric field limit reveals that direct tunneling always dominates over indirect tunneling in Ge. The impact of the direct transition in Ge on the performance of two realistic tunnel field-effect transistor configurations is illustrated with TCAD simulations. The influence of field-induced quantum confinement is included in the analysis based on a back-of-the-envelope calculation.

Modeling the single-gate, double-gate, and gate-all-around tunnel field-effect transistor

Tunnel field-effect transistors (TFETs) are potential successors of metal-oxide-semiconductor FETs because scaling the supply voltage below 1 V is possible due to the absence of a subthreshold-swing limit of 60 mV/decade. The modeling of the TFET performance, however, is still preliminary. We have developed models allowing a direct comparison between the single-gate, double-gate, and gate-all-around configuration at high drain voltage, when the drain-voltage dependence is negligible, and we provide improved insight in the TFET physics. The dependence of the tunnel current on device parameters is analyzed, in particular, the scaling with gate-dielectric thickness, channel thickness, and dielectric constants of gate dielectric and channel material. We show that scaling the gate-dielectric thickness improves the TFET performance more than scaling the channel thickness and that improvements are often overestimated. There is qualitative agreement between our model and our experimental data.

Analytical model for point and line tunneling in a tunnel field-effect transistor

The tunnel field-effect transistor (TFET) is a promising candidate for the succession of the MOSFET at nanometer dimensions. In general, the TFET current can be decomposed into two components referred to as point tunneling and line tunneling. In this paper we derive a compact analytical model for the current due to point tunneling complementing the previously derived analytical model for line tunneling. We show that the derived analytical expression for point tunneling provides a more consistent estimate of the TFET current than a commercial device simulator. Both the line and point tunneling current do not show a fixed subthreshold-slope. Three key parameters for design of a TFET are: bandgap, dielectric thickness and source doping level. A small bandgap is beneficial for a high TFET on-current and a low onset voltage. Point tunneling and line tunneling show a strong dependance on gate dielectric thickness and doping concentration respectively.

Analytical model for a tunnel field-effect transistor

The tunnel field-effect transistor (TFET) is a promising candidate for the succession of the MOSFET at nanometer dimensions. Due to the absence of a simple analytical model for the TFET, the working principle is generally not well understood. In this paper a new TFET structure is introduced and using Kanepsilas model, an analytical expression for the current through the TFET is derived. Furthermore, a compact expression for the TFET current is derived and conclusions concerning TFET design are drawn. The obtained analytical expressions are compared with results from a 2D device simulator and good agreement at low gate voltages is demonstrated.

Optimization of Gate-on-Source-Only Tunnel FETs With Counter-Doped Pockets

We investigate a promising tunnel FET configuration having a gate on the source only, which is simultaneously exhibiting a steeper subthreshold slope and a higher ON-current than the lateral tunneling configuration with a gate on the channel. Our analysis is performed based on a recently developed 2-D quantum-mechanical simulator calculating band-to-band tunneling and including quantum confinement (QC). It is shown that the two disadvantages of the structure, namely, the sensitivity to gate alignment and the physical oxide thickness, are mitigated by placing a counter-doped parallel pocket underneath the gate-source overlap. The pocket also significantly reduces the field-induced QC. The findings are illustrated with all-Si and all-Ge gate-onsource-only tunnel field-effect transistor simulations.

Temperature-Dependent Modeling and Characterization of Through-Silicon Via Capacitance

A semianalytical model of the through-silicon via (TSV) capacitance for elevated operating temperatures is derived and verified with electrical measurements. The effect of temperature on the increase in TSV capacitance over different technology parameters is explored, and it is shown that higher oxide thickness reduces the impact of temperature rise on TSV capacitance, while with low doped substrates, which are instrumental for reducing the TSV capacitance, the sensitivity of TSV capacitance to temperature is large and cannot be ignored.

Physical modeling of strain-dependent hole mobility in Ge p-channel inversion layers

We present comprehensive calculations of the low-field hole mobility in Ge p-channel inversion layers with SiO2 insulator using a six-band k⋅p band-structure model. The cases of relaxed, biaxially, and uniaxially (both tensily and compressively) strained Ge are studied employing an efficient self-consistent method—making use of a nonuniform spatial mesh and of the Broyden second method—to solve the coupled envelope-wave function k⋅p and Poisson equations. The hole mobility is computed using the Kubo–Greenwood formalism accounting for nonpolar hole-phonon scattering and scattering with interfacial roughness. Different approximations to handle dielectric screening are also investigated. As our main result, we find a large enhancement (up to a factor of 10 with respect to Si) of the mobility in the case of uniaxial compressive stress similarly to the well-known case of Si. Comparison with experimental data shows overall qualitative agreement but with significant deviations due mainly to the unknown morpholog...

Calculation of the electron mobility in III-V inversion layers with high-κ dielectrics

We calculate the electron mobility for a metal-oxide-semiconductor system with a metallic gate, high-κ dielectric layer, and III-V substrate, including scattering with longitudinal-optical (LO) polar-phonons of the III-V substrate and with the interfacial excitations resulting from the coupling of insulator and substrate optical modes among themselves and with substrate plasmons. In treating scattering with the substrate LO-modes, multisubband dynamic screening is included and compared to the dielectric screening in the static limit and with the commonly used screening model obtained by defining an effective screening wave vector. The electron mobility components limited by substrate LO phonons and interfacial modes are calculated for In0.53Ga0.47As and GaAs substrates with SiO2 and HfO2 gate dielectrics. The mobility components limited by the LO-modes and interfacial phonons are also investigated as a function of temperature. Scattering with surface roughness, fixed interface charge, and nonpolar-phonons...

InGaAs tunnel diodes for the calibration of semi-classical and quantum mechanical band-to-band tunneling models

Promising predictions are made for III-V tunnel-field-effect transistor (FET), but there is still uncertainty on the parameters used in the band-to-band tunneling models. Therefore, two simulators are calibrated in this paper; the first one uses a semi-classical tunneling model based on Kanes formalism, and the second one is a quantum mechanical simulator implemented with an envelope function formalism. The calibration is done for In0.53Ga0.47As using several p+/intrinsic/n+ diodes with different intrinsic region thicknesses. The dopant profile is determined by SIMS and capacitance-voltage measurements. Error bars are used based on statistical and systematic uncertainties in the measurement techniques. The obtained parameters are in close agreement with theoretically predicted values and validate the semi-classical and quantum mechanical models. Finally, the models are applied to predict the input characteristics of In0.53Ga0.47As n- and p-lineTFET, with the n-lineTFET showing competitive performance com...

Zener tunneling in semiconductors under nonuniform electric fields

Recently, a renewed interest in Zener tunneling has arisen because of its increasing impact on semiconductor device performance at nanometer dimensions. In this paper we evaluate the tunnel probability under the action of a nonuniform electric field using a two-band model and arrive at significant deviations from the commonly used Kane’s model, valid for weak uniform fields only. A threshold on the junction bias where Kane’s model for Zener tunneling breaks down is determined. Comparison with Kane’s model particularly shows that our calculation yields a higher tunnel probability for intermediate electric fields and a lower tunnel probability for high electric fields. When performing a current calculation comparing to the WKB approximation for the case of an abrupt p-n junction significant differences concerning the shape of the I-V curve are demonstrated.