Agathoklis Papadopoulos

FPGA-based hardware acceleration for local complexity analysis of massive genomic data

While genomics have significantly advanced modern biological achievements, it requires extensive computational power, traditionally employed on large-scale cluster machines as well as multi-core systems. However, emerging research results show that FPGA-based acceleration of algorithms for genomic applications greatly improves the performance and energy efficiency when compared to multi-core systems and clusters. In this work, we present a parallel, hardware acceleration architecture of the CAST (Complexity Analysis of Sequence Tracts) algorithm, employed by biologists for complexity analysis of protein sequences encoded in genomic data. CAST is used for detecting (and subsequently masking) low-complexity regions (LCRs) in protein sequences. We designed and implemented the CAST accelerator architecture and built an FPGA prototype, with the purpose of benchmarking its performance against serial and multithreaded implementations of the CAST algorithm in software. The proposed architecture achieves remarkable speedup compared to both serial and multithreaded software CAST implementations ranging from approx. 100x-5000x, depending on the system configuration and the dataset features, such as low-complexity content and sequence length distribution. Such performance may enable complex analyses of voluminous sequence datasets, and has the potential to interoperate with other hardware architectures for protein sequence analysis.

Opportunities from the use of FPGAs as platforms for bioinformatics algorithms

This paper presents an in-depth look of how FPGA computing can offer substantial speedups in the execution of bioinformatics algorithms, with specific results achieved to date for a broad range of algorithms. Examples and case studies are presented for sequence comparison (BLAST, CAST), multiple sequence alignment (MAFFT, T-Coffee), RNA and protein secondary structure prediction (Zuker, Predator), gene prediction (Glimmer/GlimmerHMM) and phylogenetic tree computation (RAxML), running on mainstream FPGA technologies as well as high-end FPGA-based systems (Convey HC1, BeeCube). This work also presents technological and other obstacles that need to be overcome in order for FPGA computing to become a mainstream technology in Bioinformatics.

A high performance hardware architecture for portable, low-power retinal vessel segmentation

Abstract The retina of the human eye and more particularly the retinal blood vasculature can be used in several medical and biometric applications. The use of retinal images in such applications however, is computationally intensive, due to the high complexity of the algorithms used to extract the vessels from the retina. In addition, the emergence of portable biometric authentication applications, as well as onsite biomedical diagnostics raises the need for real-time, power-efficient implementations of such algorithms that can also satisfy the performance and accuracy requirements of portable systems that use retinal images. In an attempt to meet those requirements, this work presents a VLSI implementation of a retina vessel segmentation system while exploring various parameters that affect the power consumption, the accuracy and performance of the system. The proposed design implements an unsupervised vessel segmentation algorithm which utilizes matched filtering with signed integers to enhance the difference between the blood vessels and the rest of the retina. The design accelerates the process of obtaining a binary map of the vessels tree by using parallel processing and efficient resource sharing, achieving real-time performance. The design has been verified on a commercial FPGA platform and exhibits significant performance improvements (up to 90×) when compared to other existing hardware and software implementations, with an overall accuracy of 92.4%. Furthermore, the low power consumption of the proposed VLSI implementation enables the proposed architecture to be used in portable systems, as it achieves an efficient balance between performance, power consumption and accuracy.

Reconfiguring the Bioinformatics Computational Spectrum: Challenges and Opportunities of FPGA-Based Bioinformatics Acceleration Platforms

This paper conducts a detailed survey on the use of FPGA-based reconfigurable computing platforms for a wide range of sequence and structural bioinformatics applications, with emphasis on performance and energy savings of the underlying architectures. Applications considered include sequence comparison, multiple sequence alignment, RNA and protein secondary structure prediction, gene prediction, and phylogenetic tree computation.

GPU technology as a platform for accelerating local complexity analysis of protein sequences

The use of GPGPU programming paradigm (running CUDA-enabled algorithms on GPU cards) in Bioinformatics showed promising results [1]. As such a similar approach can be used to speedup other algorithms such as CAST, a popular tool used for masking low-complexity regions (LCRs) in protein sequences [2] with increased sensitivity. We developed and implemented a CUDA-enabled version (GPU_CAST) of the multi-threaded version of CAST software first presented in [3] and optimized in [4]. The proposed software implementation uses the nVIDIA CUDA libraries and the GPGPU programming paradigm to take advantage of the inherent parallel characteristics of the CAST algorithm to execute the calculations on the GPU card of the host computer system. The GPU-based implementation presented in this work, is compared against the multi-threaded, multi-core optimized version of CAST [4] and yielded speedups of 5x-10x for large protein sequence datasets.

Towards systolic hardware acceleration for local complexity analysis of massive genomic data

Modern biological research has greatly benefited from genomics. Such research however requires extensive computational power, traditionally employed on large-scale cluster machines as well as multi-core systems. Recent research in reconfigurable architectures however suggests that FPGA-based acceleration of genomic algorithms greatly improves the performance and energy efficiency when compared to multi-core systems and clusters. In this work, we present an initial attempt for massive systolic acceleration of the popular CAST algorithm employed by biologists for complexity analysis of genomic data. CAST is used for detecting (and subsequently masking) low-complexity regions (LCRs) in protein sequences. We designed and implemented a high-performance hardware-accelerated version of CAST for which we built an FPGA prototype, and benchmarked its performance against serial and multithreaded versions of the CAST algorithm in software. The proposed architecture achieves remarkable speedup compared to both serial and multithreaded CAST implementations ranging from approx. 100x-9500x, depending on the dataset features, such as low-complexity content and sequence length distribution. Such performance may enable complex analyses of voluminous sequence datasets, and has the potential to interoperate with other hardware architectures for protein sequence analysis.

A reconfigurable MPSoC-based QAM modulation architecture

QAM is a widely used multi-level modulation technique, with a variety of applications in data radio communication systems. Most existing implementations of QAM-based systems use high levels of modulation in order to meet the high data rate constraint of emerging applications. This work presents the architecture of a highly-parallel MPSoC-based QAM modulator that offers multi-rate modulation. The proposed MPSoC architecture is modular and provides flexibility via dynamic reconfiguration of the QAM, offering high data rates (more than 1 Gbps), even at low modulation levels (16-QAM). Furthermore, the proposed QAM implementation integrates a hardware-based resource allocation algorithm for dynamic load balancing.

Towards hardware-accelerated suffix array construction architecture for the de novo DNA sequence assembly

It has been proven that bioinformatics applications can greatly benefit from hardware acceleration, and the de novo DNA sequence assembly is one of the most biologically significant bioinformatics problems. However, sequence assembly consists of a number of computation- and memory-intensive processing steps. This paper presents an initial approach towards an efficient hardware accelerator that will minimize the assembly time while reducing the energy footprint of the application. In particular, we present a hardware architecture, validated using an FPGA, for the suffix array construction as a first step towards a hardware-accelerated de novo DNA sequence assembler. This exploratory implementation allows us to extract information about the benefits and challenges, and provides indicative hardware utilization, memory management and I/O between the host system and the targeted FPGA.

GPU technology as a platform for accelerating physiological systems modeling based on Laguerre-Volterra networks.

The use of a GPGPU programming paradigm (running CUDA-enabled algorithms on GPU cards) in biomedical engineering and biology-related applications have shown promising results. GPU acceleration can be used to speedup computation-intensive models, such as the mathematical modeling of biological systems, which often requires the use of nonlinear modeling approaches with a large number of free parameters. In this context, we developed a CUDA-enabled version of a model which implements a nonlinear identification approach that combines basis expansions and polynomial-type networks, termed Laguerre-Volterra networks and can be used in diverse biological applications. The proposed software implementation uses the GPGPU programming paradigm to take advantage of the inherent parallel characteristics of the aforementioned modeling approach to execute the calculations on the GPU card of the host computer system. The initial results of the GPU-based model presented in this work, show performance improvements over the original MATLAB model.

Towards optimal CMOS lifetime via unified reliability modeling and multi-objective optimization

Reliability of CMOS devices emerges as a vital design constraint, evidenced by several CMOS failure mechanisms. Such mechanisms have traditionally been modeled independently, using statistical approximation techniques to estimate Mean-Time-to-Failure (MTTF) rates. This paper proposes a unified framework that integrates the existing failure models into a multi-objective optimization engine, in an attempt to provide a pareto-optimal solution indicating the suggested operating conditions of a system for a given technology and size (in transistors), in an effort to maximize its lifetime reliability. In addition to the existing failure mechanisms, the framework also considers a proposed system-level leakage power estimation model, as leakage is interdependent on temperature, and as such impacts system reliability. The framework can be used in several design scenarios, such as thermal-aware task scheduling.