Ahmad Abedin

Optimization of SiGe selective epitaxy for source/drain engineering in 22 nm node complementary metal-oxide semiconductor (CMOS)

SiGe has been widely used for source/drain (S/D) engineering in pMOSFETs to enhance channel mobility. In this study, selective Si1−xGex growth (0.25 ≤ x ≤ 0.35) with boron concentration of 1–3 × 1020 cm−3 in the process for 22 nm node complementary metal-oxide semiconductor (CMOS) has been investigated and optimized. The growth parameters were carefully tuned to achieve deposition of high quality and highly strained material. The thermal budget was decreased to 800 °C to suppress dopant diffusion, to minimize Si loss in S/D recesses, and to preserve the S/D recess shape. Two layers of Si1−xGex were deposited: a bottom layer with high Ge content (x = 0.35) which filled the recess and a cap layer with low Ge content (x = 0.25) which was elevated in the S/D regions. The elevated SiGe cap layer was intended to be consumed during the Ni-silicidation process in order to avoid strain reduction in the channel region arising from strain relaxation in SiGe S/D. In this study, a kinetic gas model was also applied to...

Impact of pattern dependency of SiGe layers grown selectively in source/drain on the performance of 22 nm node pMOSFETs

Pattern dependency of selective epitaxy of Si1 xGex (0.20 6 x 6 0.45) grown in recessed source/drain regions of 22 nm pMOSFETs has been studied. A complete substrate mapping over 200 mm wafers was performed and the transistors’ characteristics were measured. The designed SiGe profile included a layer with Ge content of 40% at the bottom of recess (40 nm) and capped with 20% Ge as a sacrificial layer (20 nm) for silicide formation. The induced strain in the channel was simulated before and after silicidation. The variation of strain was localized and its effect on the transistors’ performance was determined. The chips had a variety of SiGe profile depending on their distance (closest, intermediate and central) from the edge of the 200 mm wafer. SiGe layers with poor epi-quality were observed when the coverage of exposed Si of the chip was below 1%. This causes high Ge contents with layer thicknesses above the

Formation of nickel germanides from Ni layers with thickness below 10 nm

The authors have studied the reaction between a Ge (100) substrate and thin layers of Ni ranging from 2 to 10 nm in thickness. The formation of metal-rich Ni5Ge3 was found to precede that of the mo ...