Per-Erik Hellström

Lateral encroachment of Ni-silicides in the source/drain regions on ultrathin silicon-on-insulator

Lateral growth of Ni silicide towards the channel region of metal-oxide-semiconductor transistors (MOSFETs) fabricated on ultrathin silicon-on-insulator (SOI) is characterized using SOI wafers with a 20-nm-thick surface Si layer. With a 10-nm-thick Ni film for silicide formation, p-channel MOSFETs displaying ordinary device characteristics with silicided p+ source/drain regions were demonstrated. No lateral growth of NiSix under gate isolation spacers was found according to electron microscopy. When the Ni film was 20 nm thick, Schottky contact source/drain MOSFETs showing typical ambipolar characteristics were obtained. A severe lateral encroachment of NiSix into the channel region leading to an increased gate leakage was revealed, while no detectable voiding at the silicide front towards the Si channel was observed.

SB-MOSFETs in UTB-SOI Featuring PtSi Source/Drain With Dopant Segregation

MOSFETs of both polarities with PtSi-based Schottky-barrier source/drain (S/D) have been fabricated in ultrathin-body Si-on-insulator. The PtSi is formed in the S/D regions without lateral silicide growth under the gate spacers. This design leads to a 30-nm underlap between the PtSi-Si contacts and the gate edges resulting in low drive currents. Despite the underlap, excellent performance is achieved for both types of MOSFETs with large drive currents and low leakage by means of dopant segregation through As and B implantation into the PtSi followed by drive-in annealing at low temperatures.

Performance Fluctuation of FinFETs With Schottky Barrier Source/Drain

A considerable performance fluctuation of FinFETs featuring PtSi-based Schottky barrier source/drain is found. The Fin-channels measure 27-nm tall and 35-nm wide. Investigation of similarly processed transistors of broad gate-widths reveals a large variation in the position of the PtSi/Si interface with reference to the gate edge along the gate width. This variation suggests an uneven underlap between the PtSi and the gate from device to device for the FinFETs, since essentially only one silicide grain would be in contact with each Fin-channel at the PtSi/Si interface. The size of the underlap is expected to sensitively affect the performance of the FinFETs.

Effects of Carbon on Schottky Barrier Heights of NiSi Modified by Dopant Segregation

The presence of carbon at the interface between NiSi and Si has been found to participate in the process of modification of effective Schottky barrier heights using the dopant segregation (DS) method. Carbon alone results in an increased phibn from 0.7 to above 0.9 eV. Boron diffusion in NiSi is inhibited by carbon, and no B-DS at the NiSi/Si interface occurs below 600degC. Above this temperature, B-DS at this interface is evident thus keeping phibn high. The presence of interfacial carbon leads to an increased interfacial As concentration resulting in beneficial effects in tuning phibp above 1.0 eV by As-DS.

Hole effective mass in silicon inversion layers with different substrate orientations and channel directions

We explore the possibility to define an effective mass parameter to describe hole transport in inversion layers in bulk MOSFETs and silicon-on-insulator devices. To do so, we employ an accurate and computationally efficient self-consistent simulator based on the six-band k·p model. The valence band structure is computed for different substrate orientations and silicon layer thicknesses and is then characterized through the calculation of different effective masses taking account of the channel direction. The effective masses for quantization and density of states are extracted from the computed energy levels and subband populations, respectively. For the transport mass, a weighted averaging procedure is introduced and justified by comparing the results with hole mobility from experiments and simulations.

Control of Self-Heating in Thin Virtual Substrate Strained Si MOSFETs

This paper presents the first results and analysis of strained Si n-channel MOSFETs fabricated on thin SiGe virtual substrates. Significant improvements in electrical performance are demonstrated compared with Si control devices. The impact of SiGe device self-heating is compared for strained Si MOSFETs fabricated on thin and thick virtual substrates. This paper demonstrates that by using high-quality thin virtual substrates, the compromised performance enhancements commonly observed in short-gate-length MOSFETs and high-bias conditions due to self-heating in conventional thick virtual substrate devices are eradicated. The devices were fabricated with a 2.8-nm gate oxide and included NiSi to reduce the parasitic series resistance. The strained layers grown on the novel substrates comprising 20% Ge did not relax during fabrication. Good on-state performance, off-state performance, and cross-wafer uniformity are demonstrated. The results show that thin virtual substrates have the potential to circumvent the major issues associated with conventional virtual substrate technology. A promising solution for realizing high-performance strained Si devices suitable for a wide range of applications is thus presented

Thulium Silicate Interfacial Layer for Scalable High-k/Metal Gate Stacks

Interfacial layer (IL) control in high-k/metal gate stacks is crucial in achieving good interface quality, mobility, and reliability. A process is developed for the formation of a thulium silicate IL that can be integrated as a replacement for conventional chemical oxide ILs in gate-last high-k/metal gate CMOS process. A straightforward process integration scheme for thulium silicate IL is demonstrated, based on self-limiting silicate formation in inert gas atmosphere and with good selectivity of the etching step. The thulium silicate IL is shown to provide 0.25±0.15 nm equivalent oxide thickness of the IL while preserving excellent electrical quality of the interface with Si. An interface state density ~0.7-2×1011 cm-2eV-1 was obtained at flat-band condition, and the nFET and pFET subthreshold slopes were 70 mV/dec. The inversion layer mobility was 20% higher than for the reference SiOx/HfO2 gate stack. Specifically, the measured mobility values were 230 cm2/Vs for nFET and 60 cm2/Vs for pFET devices, at an inversion charge density of 1013 cm-2 and at a total capacitance equivalent thickness of 1.6 nm.

Electrically robust ultralong nanowires of NiSi, Ni2Si and Ni31Si12

Mass fabrication of directly accessible, ultralong, uniform Si nanowires is realized by employing a controllable and reproducible method based on standard Si technology. High-conductivity polycrystalline Ni-silicide nanowires around 30 nm by 30 nm in cross section, able to support extremely high currents at ∼108A∕cm2, are obtained by means of solid-state reaction of the Si nanowires with subsequently deposited Ni films. By properly adjusting the Ni film thickness, NiSi, Ni2Si, and Ni31Si12 nanowires characterized with distinct resistivity and temperature coefficient of resistance are obtained. Upon annealing, the electrical continuity of the nanowires breaks at temperatures about 0.7 times the melting points of the silicides.

Characterization of transfer bonded silicon bolometer arrays

In this paper we present the design, fabrication and characterization of arrays of boron doped polycrystalline silicon bolometers. The bolometer arrays have been fabricated using CMOS compatible wafer-level transfer bonding. The transfer bonding technique allows the bolometer materials to be deposited and optimized on a separate substrate and then, in a subsequent integration step to be transferred to the read-out integrated circuit (ROIC) wafer. Transfer bonding allows thermal infrared detectors with crystalline and/or high temperature deposited, high performance temperature sensing materials to be integrated on CMOS based ROICs. Uncooled infrared bolometer arrays with 18x18 pixels and with 320x240 pixels have been fabricated on silicon substrates. Individual pixels of the arrays can be addressed for characterization purposes. The resistance of the bolometers has been measured to be in the 50 kΩ range and the temperature coefficient of resistance (TCR) of the bolometer has been measured to be -0.52%/K. The pixel structure is designed as a resonant absorbing cavity, with expected absorbance above 90%, in the wavelength interval of 8 to 12 μm. The measured results are in good agreement with the predicted absorbance values.

Fully Depleted UTB and Trigate N-Channel MOSFETs Featuring Low-Temperature PtSi Schottky-Barrier Contacts With Dopant Segregation

Schottky-barrier source/drain (SB-S/D) presents a promising solution to reducing parasitic resistance for device architectures such as fully depleted UTB, trigate, or FinFET. In this letter, a low-temperature process (< 700degC) with PtSi-based S/D is examined for the fabrication of n-type UTB and trigate FETs on SOI substrate (tSi = 30 nm). Dopant segregation with As was used to achieve the n-type behavior at implantation doses of 1 ldr 1015 and 5 ldr 1015 cm-2. Similar results were found for UTB devices with both doses, but trigate devices with the larger dose exhibited higher on currents and smaller process variation than their lower dose counterparts.